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| 20090322667 | Data driver - A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on. | 12-31-2009 |
| 20120030549 | DATA TRANSMISSION DETECTING DEVICE, DATA TRANSMISSION DETECTING METHOD AND ELECTRONIC DEVICE THEREOF - A data transmission detecting device including a detecting module and a detection value calculating module is provided. The detecting module has a plurality of receiving terminals and receives a first data and a second data during a first period. The detecting module calculates a total detection value according to the first data and the second data, and performs an error check comparison by comparing the total detection value with an error check code. When the detecting module again receives the first data during a second period, the detection value calculating module transmits an auxiliary detection value to the detecting module, so that the detecting module calculates a corresponding total detection value according to the auxiliary detection value, and performs the error check comparison by comparing the total detection value with the error check code. The first period and the second period are two successive periods adjacent to each other. | 02-02-2012 |
| 20120062546 | DATA DRIVER - A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on. | 03-15-2012 |
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| 20090151637 | MICROWAVE-EXCITED PLASMA SOURCE USING RIDGED WAVE-GUIDE LINE-TYPE MICROWAVE PLASMA REACTOR - A microwave-excited plasma source using a ridged wave-guide line-type microwave plasma reactor is disclosed. The microwave-excited plasma source comprises a reaction chamber, a ridged wave-guide and a separation plate. The ridged wave-guide is disposed on the reaction chamber, and comprises a frame portion, a ridge portion and a line-shaped slot. The line-shaped slot is disposed on a first side of the frame portion, and the ridge portion facing the line-shaped slot is disposed on a second side of the frame portion. The separation plate is disposed on the line-shaped slot. Moreover, the ridged wave-guide is suitable for concentrating microwave power, which is transmitted to the reaction chamber through the line-shaped slot in order to excite plasma. | 06-18-2009 |
| 20100123381 | CATHODE DISCHARGE APPARATUS - A cathode discharge device is provided. The cathode discharge apparatus includes an anode, a cathode and plural cathode chambers. The cathode is located inside the anode, where the cathode has plural flow channels and at least one flow channel hole, and the plural flow channels are connected to one another through the flow channel hole. The plural cathode chambers are located inside the cathode, wherein each of the cathode chambers has a chamber outlet and a chamber inlet connected with at least one of the flow channels. | 05-20-2010 |
| 20100126418 | GAS SHOWER MODULE - A gas shower module for gas deposition chamber with gas channel is disclosed, which comprises: a distributor with at least one diffusion cell positioned therein along first axial direction and a plurality of inlets respectively connecting to the gas channel and the diffusion cell; and a shower with at least one shower channel positioned therein along second axial direction, gas-inlet passages connected to the diffusion cell and the shower channel, and gas-outlet passages connected to the shower channel and gas deposition chamber; wherein the distributor is connected to the shower so that the diffusion cell will be connected to the shower channel through gas-inlet passages and the first axial direction is not be parallel to the second axial direction. | 05-27-2010 |
| 20110079963 | VACUUM APPARATUS OF ROTARY MOTION ENTRY - A vacuum apparatus of rotary motion entry is disclosed, which comprises: a shaft sleeve, disposed on a cavity wall of a vacuum system; a rotary shaft, ensheathed by the shaft sleeve; and a transmission set, connected to the rotary shaft for driving the same; wherein, the rotary shaft is disposed passing through a hole formed on the base of the shaft sleeve while there are a first bearing, a second bearing, a sealing ring and a shaft seal being arranged separately inside the hole. Moreover, the shaft seal has a flake-like lip flange formed extending toward the center of the hole, that is capable of being extended away from the vacuum system by the inserting of the rotary shaft into the hole, and thereby, enabling the lip flange to engage with the rotary shaft tightly by the atmospheric pressure and thus isolating the outside world from the vacuum system. | 04-07-2011 |
| 20120070590 | PLASMA ENHANCED ATOMIC LAYER DEPOSITION APPARATUS AND THE CONTROLLING METHOD THEREOF - This prevent disclosure provides a plasma enhanced atomic layer deposition apparatus and the controlling method thereof. The plasma enhanced atomic layer deposition apparatus includes: a plurality of reaction chambers, each of the reaction chambers having a first reaction space and a second reaction space; an adjustable partition unit controlled to separate or communicate the first and the second reaction spaces; and a plurality of heating carriers respectively disposed in the plurality of reaction chambers. The method manipulates the movement of the partition plate, leading to separation or communication between the first and second reaction spaces, so as to avoid the interference or inter-reaction between process gases and the resultant particles contaminating the substrates. | 03-22-2012 |
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| 20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 12-04-2008 |
| 20100006924 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region. | 01-14-2010 |
| 20100073985 | METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage. | 03-25-2010 |
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| 20100318687 | METHOD AND APPARATUS FOR FORMATTING NETWORK-ATTACHED STORAGE - A method for formatting a network-attached storage (NAS) includes: coupling the NAS to a user-end personal computer (PC) via an external bus which supports a plug and play function; and utilizing the user-end PC to format a storage device of the NAS via the external bus. A network-attached storage includes a storage device, and a bus interface for coupling an external bus which supports a plug and play function such that the storage device of the NAS is formatted via the external bus. | 12-16-2010 |
| 20110173288 | NETWORK STORAGE SYSTEM AND RELATED METHOD FOR NETWORK STORAGE - A network storage system includes a first data buffer, a second data buffer, a pre-allocating module and a control module. The first data buffer is utilized for storing a storage data received from a network-base. The second data buffer is coupled to the first data buffer and includes a plurality of data buffering units. The pre-allocating module is coupled to the second data buffer and utilized for allocating the plurality of data buffering units to the second data buffer in advance. The control module controls the first data buffer to write the stored storage data into the plurality of data buffering units. | 07-14-2011 |
| 20120066414 | NETWORK STORAGE SYSTEM AND NETWORK STORAGE METHOD - The present invention provides a network storage system for increasing data writing efficiency of a net storage service and a network storage method for increasing data writing efficiency of the net storage service. The network storage system comprises: a first module, a first data buffer, a second module, and a third module. The present invention can omit the standard process of the traditional operation system processing files when writing data, and the network storage system and the network storage method of the present invention can use a new file processing procedure in the second module and the third module. In this way, the present invention can shorten the file processing flow in the traditional network storage system, so as to increase data writing efficiency of the net storage service over 50%. | 03-15-2012 |
| 20120102230 | NETWORK STORAGE SYSTEM AND NETWORK STORAGE METHOD - The present invention provides a network storage system for increasing data reading efficiency of a net storage service and a network storage method for increasing data reading efficiency of the net storage service. The network storage system comprises: a network processing module, a first fast file transmitting module, and a second fast file transmitting module. The present invention can omit the standard process of the traditional operation system processing files when reading data, and the network storage system and the network storage method of the present invention can use a new file processing procedure in the second fast file transmitting module. In this way, the present invention can shorten the file processing flow in the traditional network storage system, so as to increase data reading efficiency of the net storage service over 250%. | 04-26-2012 |
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| 20080278337 | URINE DETECTION SYSTEM AND METHOD - A urine detection system is provided for detecting degree of wetness of a diaper, comprising a plane printing electrode, a sensor, and a display unit. The plane printing electrode comprises a first electrode area and a second electrode area. The sensor comprises a first sensor electrode, a second sensor electrode and a processor. Wherein the first sensor electrode and the first electrode area forms a first capacitor, and the second sensor electrode and the second electrode area forms a second capacitor. The processor, detects capacitance of the first and second capacitors, and determines a signal representing degree of wetness of the diaper. The display unit receives the signal and displays the degree of wetness corresponding to the signal. | 11-13-2008 |
| 20080315433 | SELF-ALIGNED WAFER OR CHIP STRUCTURE, SELF-ALIGNED STACKED STRUCTURE AND METHODS FOR FABIRCATING THE SAME - A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface. | 12-25-2008 |
| 20090121299 | Wafer level sensing package and manufacturing process thereof - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 05-14-2009 |
| 20090124074 | WAFER LEVEL SENSING PACKAGE AND MANUFACTURING PROCESS THEREOF - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 05-14-2009 |
| 20090161901 | ULTRA THIN PACKAGE FOR ELECTRIC ACOUSTIC SENSOR CHIP OF MICRO ELECTRO MECHANICAL SYSTEM - An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed. | 06-25-2009 |
| 20110150261 | CAPACITIVE TRANSDUCER AND FABRICATION METHOD - A capacitive transducer and fabrication method are disclosed. The capacitive transducer includes a substrate, a first electrode mounted on the substrate, a cap having a through-hole and a cavity beside the through-hole, a second electrode mounted on the cap across the through-hole. The second electrode is deformable in response to pressure fluctuations applied thereto via the through-hole and defines, together with the first electrode, as a capacitor. The capacitor includes a capacitance variable with the pressure fluctuations and the cavity defines a back chamber for the deformable second electrode. | 06-23-2011 |
| 20110297434 | VACUUM HERMETIC ORGANIC PACKAGING CARRIER - A vacuum hermetic organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier. | 12-08-2011 |
