| Patent application number | Description | Published |
|---|
| 20080205183 | SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage. | 08-28-2008 |
| 20100109753 | METHOD OF OUTPUTTING TEMPERATURE DATA IN SEMICONDUCTOR DEVICE AND TEMPERATURE DATA OUTPUT CIRCUIT THEREFOR - A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation. | 05-06-2010 |
| 20100309742 | METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY - Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports. | 12-09-2010 |
| 20100314772 | Stacked Layer Type Semiconductor Device and Semiconductor System Including the Same - A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1. | 12-16-2010 |
| 20100322021 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal. | 12-23-2010 |
| 20110007576 | SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY SEMICONDUCTOR DEVICE FOR CONTROLLING OUTPUT DATA - Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers. | 01-13-2011 |
| 20110090754 | INTERNAL POWER GENERATING APPARATUS, MULTICHANNEL MEMORY INCLUDING THE SAME, AND PROCESSING SYSTEM EMPLOYING THE MULTICHANNEL MEMORY - An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states. | 04-21-2011 |
| 20110093235 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip. | 04-21-2011 |
| 20110095373 | SEMICONDUCTOR CHIP, STACK MODULE, AND MEMORY CARD - Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV. | 04-28-2011 |
| 20110095814 | CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT - An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal. | 04-28-2011 |
| 20110107006 | Multiprocessor system and method thereof - A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port. | 05-05-2011 |
