Patent application number | Description | Published |
20080252502 | DELTA-SIGMA AD CONVERTER APPARATUS USING DELTA-SIGMA MODULATOR CIRCUIT PROVIDED WITH RESET CIRCUIT RESETTING INTEGRATOR - In a delta-sigma modulator circuit, an integrator integrates an input signal, and a quantization circuit quantizes the integrated signal with a predetermined quantization number, and outputs a quantization result signal. A DA converter circuit outputs an analog signal indicating a DA conversion result based on the quantization result signal. An oscillation detector circuit detects that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal. A reset circuit resets the integrator based on the oscillation detection signal. | 10-16-2008 |
20090002088 | DIGITAL CONTROLLED OSCILLATOR, FREQUENCY SYNTHESIZER, RADIO COMMUNICATION APPARATUS USING THE SAME, AND CONTROL METHOD FOR THE SAME - The digital controlled oscillator includes a variable capacitance section having a first capacitor array of a plurality of first variable capacitors and a second capacitor array of a plurality of second variable capacitors, and generates a signal having an oscillation frequency corresponding to the capacitance value of the variable capacitance section. The first capacitance change amount in the individual first variable capacitors is a value obtained by multiplying the second capacitance change amount in the individual second variable capacitors by an integer equal to or more than 2, and the number of second variable capacitors is equal to or more than a value obtained by subtracting 1 from the integer equal to or more than 2. | 01-01-2009 |
20090079511 | Polar Modulation Transmission Circuit and Communication Device - A transmission circuit for outputting transmission signals with a low distortion and a high efficiency over a wide range of output power is provided. A signal generation section ( | 03-26-2009 |
20090115523 | DISCRETE TIME AMPLIFIER CIRCUIT AND ANALOG-DIGITAL CONVERTER - The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle). | 05-07-2009 |
20090302918 | CLOCK SIGNAL GENERATION APPARATUS - A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components. | 12-10-2009 |
20090315604 | CLOCK SIGNAL GENERATION APPARATUS AND DISCRETE-TIME CIRCUIT - In a clock signal generation apparatus, a clock signal delay calculation section has a delay detection circuit for monitoring the delay characteristics of the variable delay circuits of a clock signal generation circuit due to external variation factors and calculates the delay amounts of N-phase clock signals, and a clock signal delay control section varies the delay amounts of the variable delay circuits on the basis of delay variation data, external variation factors being used as parameters thereof, stored in a delay variation data section and the calculated delay amounts of the N-phase clock signals. In the case that, for example, clock signals required for a discrete-time circuit have changed due to external variation factors, such as power supply voltage and environmental temperature, the non-overlap times and the duty ratios of the clock signals required for the discrete-time circuit can be set to optimal values. | 12-24-2009 |
20100066416 | DIGITALLY-CONTROLLED OSCILLATOR, FREQUENCY SYNTHESIZER AND RADIO COMMUNICATION DEVICE - A frequency synthesizer includes a digitally-controlled oscillator and an oscillation frequency control unit. The digitally-controlled oscillator includes a loop-shaped transmission line path having an odd number of parallel portions in each of which two conductors are arranged in parallel to each other with a space therebetween, and an odd number of intersection portions in each of which two conductors intersect spatially, an active circuit coupled between the two conductors, and a first variable capacitance unit and a second variable capacitance unit. The oscillation frequency control unit includes a ΣΔ modulation circuit for subjecting to ΣΔ modulation a first control signal for switching a high capacitance state and a low capacitance state of a first variable capacitance element included in the first variable capacitance unit. | 03-18-2010 |
20100214142 | DELTA SIGMA A/D MODULATOR - A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time. | 08-26-2010 |