| Patent application number | Description | Published |
|---|
| 20080227273 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) forming a first groove exposing a side of the first semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; d) forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the first groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; e) respectively forming a third semiconductor layer on an upper surface of the semiconductor substrate and a lower surface of the second semiconductor layer that are facing an inside of the cavity while leaving a space in the cavity; and f) thermally oxidizing the third semiconductor layer so as to form a buried oxide film in the cavity. | 09-18-2008 |
| 20080233708 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a semiconductor substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; forming a support covering the second semiconductor layer from inside of the first groove to a surface of the second semiconductor layer so as to support the second semiconductor layer; etching a sidewall formed in the first groove of the support so as to render the sidewall thin; forming a second groove exposing the first semiconductor layer by sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer; forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the second groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; and forming a buried oxide film by thermally oxidizing an upper surface of the semiconductor substrate and a lower surface of the second semiconductor layer that are facing inside of the cavity. | 09-25-2008 |
| 20080237715 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device, includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer so as to form a first groove exposing the first semiconductor layer; d) forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the first groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; e) thermally oxidizing each of an upper surface of the semiconductor substrate and a lower surface of the second semiconductor layer while leaving a gap in the cavity so as to form oxide films on an upside and a downside of the gap; and f) forming an insulation etching stopper layer in the gap that is sandwiched by the oxide films from a top and a bottom. | 10-02-2008 |
| 20080242036 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device, includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer so as to form a first groove exposing the first semiconductor layer; d) forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the first groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; e) forming an embedded oxide film in the cavity; f) etching the embedded oxide film from a lateral surface side thereof so as to form a gap between a peripheral part of the second semiconductor layer and the semiconductor substrate; and g) forming an insulating etching stopper layer in the gap. | 10-02-2008 |
| Patent application number | Description | Published |
|---|
| 20080239127 | Method and apparatus for processing a pixel signal - An NchMOS transistor Q | 10-02-2008 |
| 20090086067 | SOLID-STATE IMAGING DEVICE, DRIVING CONTROL METHOD THEREOF, AND IMAGING APPARATUS - A solid-state imaging includes a comparing circuit, an inverting circuit, and a masking circuit, and performs column parallel AD conversion processing of analog pixel signals outputted from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit is canceling an input offset between the pixel signal and the reference signal. | 04-02-2009 |
| 20090219428 | SOLID STATE IMAGE CAPTURING APPARATUS AND CAMERA APPARATUS - A solid state image capturing apparatus is disclosed. A pixel array section has unit pixels containing photoelectric conversion elements, the unit pixels being two-dimensionally arranged in a matrix, and column signal wires correspondingly to columns of the matrix of the unit pixels. A line scanning section selectively controls lines of the matrix of the unit pixels of the pixel array section. An analog-to-digital conversion section converts an analog signal outputted from unit pixels of a line of the matrix of the unit pixels selected by the line scanning section through a corresponding column signal line to a digital signal. A conversion clock supply section selectively generates a conversion clock having a first clock period or a second clock period. An addition section adds unit pixel digital signals converted in the analog-to-digital conversion section by the conversion clocks having the first clock period and the second clock period, respectively. | 09-03-2009 |
| 20090278969 | SOLID-STATE IMAGE PICKUP DEVICE AND CAMERA SYSTEM - A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line. | 11-12-2009 |
| 20100194949 | A/D CONVERSION CIRCUIT, SOLID-STATE IMAGE SENSOR, AND CAMERA SYSTEM - There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC | 08-05-2010 |
| 20110149124 | METHOD AND APPARATUS FOR PROCESSING A PIXEL SIGNAL - An NchMOS transistor Q | 06-23-2011 |
| 20110205386 | Solid-state imaging device and camera system - A solid-state imaging device including: a pixel section formed by a matrix-like array of a plurality of pixels performing photoelectric conversion; and a pixel signal readout section reading out a pixel signal from the pixel section in units for reading each formed by a plurality of pixels, wherein the pixel signal readout section includes a column-parallel type ADC group formed by a plurality of analog-digital converters (ADCs) for performing A-D conversion of a pixel reset level, and a signal processing system, the signal processing system obtaining only an average value of results of A-D conversion of pixel reset levels for a plurality of pixels and automatically adjusting an input offset value for the conversion range of the ADCs such that the average value of pixel reset levels will be adequately positioned with respect to the A-D conversion range. | 08-25-2011 |
| 20110279723 | Signal processing circuit, solid-state imaging device, and camera system - A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal. | 11-17-2011 |
| 20120008033 | SOLID-STATE IMAGE PICKUP DEVICE AND CAMERA SYSTEM - A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line. | 01-12-2012 |
