| Patent application number | Description | Published |
|---|
| 20080226333 | USED TONER COLLECTION DEVICE AND IMAGE FORMING APPARATUS - A used toner conveyance device includes a lateral conveyance member for conveying used toner substantially in the horizontal direction, and a vertical conveyance member for upwardly conveying the used toner transferred from the lateral conveyance member. The vertical conveyance member transfers the used toner to either a collection space or a next conveyance path. The vertical conveyance member stops its operation when a prescribed delay time has elapsed after the lateral conveyance member stops conveyance operation. | 09-18-2008 |
| 20080304324 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH REALIZES "1" WRITE OPERATION BY BOOSTING CHANNEL POTENTIAL - A nonvolatile semiconductor memory device includes a memory cell array having a plurality of cell units each including a preset number of memory cells and select gate transistors on drain and source sides. The nonvolatile semiconductor memory device includes a voltage control circuit to prevent occurrence of an erroneous write operation due to excessively high boost voltage of a channel when “1” is written into the memory cell. | 12-11-2008 |
| 20090109753 | NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories. | 04-30-2009 |
| 20090121208 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a plurality of first lines; a plurality of second lines crossing the plurality of first lines; a plurality of memory cells each connected at an intersection of the first and second lines between both lines and including a variable resistor operative to store information in accordance with a variation in resistance; and a protection film covering the side of the variable resistor to suppress migration of cations at the side of the variable resistor. | 05-14-2009 |
| 20090134431 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage apparatus includes: a plurality of first wirings; a plurality of second wirings which cross the plurality of first wirings; and a memory cell which is connected between both the wirings at an intersection of the first and second wirings, and includes a variable resistive element operative to store information according to a change in resistance and includes a variable resistive element, wherein the memory cell is formed so that a cross section area of the variable resistive element becomes smaller than a cross section area of the other portion. | 05-28-2009 |
| 20090137112 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - A method of manufacturing nonvolatile semiconductor memory devices comprises forming a first wiring material; and stacking memory cell materials on the first wiring material, which configure memory cells each including a variable resistor operative to nonvolatilely store information in accordance with variation in resistance. The method also comprises forming a plurality of first parallel trenches in the first wiring material and the stacked memory cell materials, the first trenches extending in a first direction, thereby forming first lines extending in the first direction and memory cell materials self-aligned with the first lines and separated by the first trenches. The method further comprises burying an interlayer insulator in the first trenches to form a block body and stacking a second wiring material on the block body. The method also comprises forming a plurality of second parallel trenches in the block body with the second wiring material stacked thereon, the second trenches extending in a second direction crossing the first direction and having a depth reaching the upper surface of the first wiring material, thereby forming second lines extending in the second direction and memory cells self-aligned with the second lines and separated by the first and second trenches. | 05-28-2009 |
| 20090141532 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other. | 06-04-2009 |
| 20090180801 | ELECTROPHOTOGRAPHIC PHOTORECEPTOR, PHOTORECEPTOR SUPPORTING DEVICE, IMAGING DEVICE AND PROCESS CARTRIDGE - An electrophotographic photoreceptor includes, a cylindrical photoreceptor pipe; at least one flange which is attached to an opening of one end of the photoreceptor pipe, and which is provided with a shaft part projecting outward from the one end at a shaft center position of the photoreceptor pipe; and an earth member which is arranged to penetrate through the shaft part of the at least one flange, and which is provided on its inward side with at least one first contact part which contacts an inner circumference of the photoreceptor pipe, and on its outward side with a second contact part. | 07-16-2009 |
| 20090185842 | CLEANING DEVICE, PROCESS CARTRIDGE, AND IMAGE FORMING APPARATUS INCLUDING SAME - A cleaning device for cleaning a surface of a rotatable image carrier includes a cleaning blade disposed to contact the image carrier and configured to remove toner on the surface of the image carrier, a lubricant applicator unit disposed above the cleaning blade, downstream from the cleaning blade in a surface rotation direction of the image carrier and configured to apply lubricant onto the surface of the image carrier, and an accumulation preventer configured to prevent the toner and excessive lubricant from the lubricant applicator unit from accumulating on the cleaning blade. | 07-23-2009 |
| 20090219740 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs. | 09-03-2009 |
| 20090268521 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded. | 10-29-2009 |
| 20100021205 | LUBRICANT APPLICATOR AND IMAGE FORMING APPARATUS INCLUDING SAME - A lubricant applicator includes a solid mold lubricant, a lubricant application roller, and a flicker member. The lubricant application roller scrapes and applies the lubricant to an image bearing member. The flicker member removes a powder substance adhered to the surface of the lubricant application roller and is disposed upstream of the solid mold lubricant in a direction of rotation of the lubricant application roller. The lubricant application roller, the flicker member, and the solid mold lubricant define a sealed space therebetween. A lubricant applicator includes the solid mold lubricant, the lubricant application roller, the flicker member, and an adherence prevention member that prevents the substance removed by the flicker member from adhering again to the lubricant application roller. A lubricant applicator includes the solid mold lubricant, the lubricant application roller, and a lubricant receiver that receives the scraped lubricant from the lubricant application roller. | 01-28-2010 |
| 20100027318 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time. | 02-04-2010 |
| 20100032725 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug. | 02-11-2010 |
| 20100034557 | Process cartridge and image forming apparatus employing same - A process cartridge detachably attached to an image forming apparatus includes a first subunit, a second subunit, a first positioning member, and a second positioning member. The first subunit accommodates a photoconductor therein. The second subunit accommodates a developer applicator therein. The photoconductor and the developer applicator are arranged substantially parallel to each other to define a development gap therebetween. The first positioning member is fastened to both the first and second subunits to position ends of the photoconductor and the developer applicator on a first side of the respective subunits. The second positioning member is fastened to only one of the first and second subunits to position ends of the photoconductor and the developer applicator on a second side of the respective subunits opposite to the first side. An image forming apparatus employing such a process cartridge is also disclosed. | 02-11-2010 |
| 20100038616 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCING METHOD THEREOF - A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction. | 02-18-2010 |
| 20100074665 | Cleaning device including cleaning mechanism having noise reduction mechanism and image forming apparatus incorporating same - A cleaning device that can be incorporated in an image forming apparatus which includes an image carrier configured to form a toner image, and a cleaning device configured to clean residual toner on the surface of the image carrier. The cleaning device includes a cleaning blade having a blade member provided to contact the surface of the image carrier and a holder to hold the blade member. The cleaning device further includes a frame to hold the cleaning blade and a vibration suppression member provided across the cleaning blade and the frame to couple the cleaning blade and the frame together and suppress vibration. | 03-25-2010 |
| 20100165740 | NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF TRIMMING AN INITIAL PROGRAM VOLTAGE FOR EACH WORD LINE - A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit. | 07-01-2010 |
| 20100187591 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction. | 07-29-2010 |
| 20100237320 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer. | 09-23-2010 |
| 20100238708 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells each provided at individual intersection between a first wiring and a second wiring, the memory cell comprising a variable resistive element, and predetermined numbers of the memory cells shearing the same first wiring to configure a page; a first control circuit configured to select a page subjected to data-writing, and to supply a constant voltage to the first wiring belonging to the selected page; a writing-voltage generating circuit configured to generate plural kinds of writing voltages for programming a resistance of the variable resistive element to one of three or more values based on a write-in data specifying three or more values; and a second control circuit configured to select the page subjected to data-writing, and to supply the writing voltages to predetermined numbers of the respective second wirings belonging to the selected page. | 09-23-2010 |
| 20100238727 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory. | 09-23-2010 |
| 20110049465 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor integrated circuit device including: multiple wiring layers stacked on a semiconductor substrate with interlayer insulating films interposed therebetween; wiring hook-up portions extended from the corresponding wirings in the respective wiring layers; and contact conductors so buried in interlayer insulating films as to pass through the hook-up portions for vertically leading wirings of the respective wiring layers, wherein the hook-up portions have different sizes from each other between at least two layers in the wiring layers. | 03-03-2011 |
| 20110068373 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n | 03-24-2011 |
| 20110134681 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory layers arranged in multi layer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs. | 06-09-2011 |
