Patent application number | Description | Published |
20130044830 | TRANSMISSION SYSTEM - A transmission system has a receiver receiving data and a request signal from a transmitter, and a monitor circuit transmitting a valid acknowledge signal to the transmitter when a received data accumulation amount in the FIFO memory is smaller than a threshold, or transmitting an invalid acknowledge signal to the transmitter when the received data accumulation amount in the FIFO memory is larger than the threshold. The transmitter transmits the request signal which is valid and the data when the acknowledge signal is valid, or stops transmission processing of the data and transmits the request signal which is invalid when the acknowledge signal is invalid, and the receiver performs reception processing of the data when the request signal is valid or stops reception processing of the data when the request signal is invalid. | 02-21-2013 |
20130162309 | RECEIVING CIRCUIT - Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit. | 06-27-2013 |
20130266055 | TRANSMISSION SYSTEM - A transmission system includes: a transmitter configured to transmit a first signal; a receiver configured to receiver a second signal from the transmitter; and a bias circuit configured to regulate a direct current bias level of an input terminal of the receiver, wherein the transmitter includes a first amplitude converter configured to convert the first signal to the second signal having a smaller amplitude than an amplitude of the first signal, wherein the receiver includes a second amplitude converter configured to convert the second signal to a third signal having a larger amplitude than the amplitude of the second signal, and wherein the first amplitude converter includes a first capacitance that restricts an amount of charge to be supplied to the receiver. | 10-10-2013 |
20130328632 | CLOCK DISTRIBUTOR AND ELECTRONIC APPARATUS - A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator. | 12-12-2013 |
20130343471 | SIGNAL TRANSMISSION CIRCUIT, SIGNAL TRANSMISSION SYSTEM, AND SIGNAL TRANSMISSION METHOD - A signal transmission circuit includes a driver circuit that includes complementary inverters, each of the complementary inverters including a plurality of transistor switches, each of the plurality of transistor switches including a pair of transistors, one of the pair of transistors operating in a saturation region and another of the pair of transistors operating in a triode region to cause a certain impedance, and that drives each of the plurality of transistor switches in accordance with complementary signals so as to output complementary voltages to a transmission line; and first voltage sources that supply operating voltages to the driver circuit so as to adjust amplitudes of the complementary voltages output from the driver circuit to the transmission line. | 12-26-2013 |
20140169442 | CLOCK DATA RECOVERY METHOD AND CLOCK DATA RECOVERY CIRCUIT - A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data. | 06-19-2014 |
20140192938 | SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals. | 07-10-2014 |
20140203852 | JITTER MONITOR - A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage. | 07-24-2014 |
20140210530 | CLOCK RECOVERY CIRCUIT AND CLOCK AND DATA RECOVERY CIRCUIT - A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock. | 07-31-2014 |
20140286469 | RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions. | 09-25-2014 |
20140376675 | RECEIVER CIRCUIT AND RECEIVING METHOD - A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase. | 12-25-2014 |
20150043695 | RECEPTION CIRCUIT - A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector. | 02-12-2015 |
20150061410 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor. | 03-05-2015 |
20150067630 | METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM - A method for designing a semiconductor integrated circuit includes: determining, by a designing device, a first wiring over which a signal is propagated and a second wiring which is not used for a propagation of the signal among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, the second wiring to be used as a wiring for storing electrical charge for an electrical charge recycling of the first wiring using the most number of the first wiring in a range that satisfies a timing constraint based on an operation rate of the signal propagated over the first wiring and a delay time of the first wiring. | 03-05-2015 |