| Patent application number | Description | Published |
| 20090172318 | Memory control device - A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories. | 07-02-2009 |
| 20090245104 | APPARATUS AND METHOD FOR CONTROLLING BUFFERING OF AN ARRIVAL PACKET - An apparatus for controlling buffering of an arrival packet. The apparatus includes a packet buffer for temporarily storing each of one or more packets to be transmitted in association with an arrival time thereof, and a packet discard section for determining an arrival packet to be discarded or to be stored in the packet buffer, based on a discard condition defined by using a packet residence time that is calculated on the basis of one or more residence times of one or more packets staying in the packet buffer, wherein the arrival packet is defined as a packet that has newly arrived at the apparatus. | 10-01-2009 |
| 20090245258 | APPARATUS AND METHOD FOR FORWARDING PACKET DATA - An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts. | 10-01-2009 |
| 20090257441 | PACKET FORWARDING APPARATUS AND METHOD FOR DISCARDING PACKETS - The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer. | 10-15-2009 |
| 20090296698 | DATA SWITCHING METHOD AND CIRCUIT - For restricting a scale increase of a switch device using a shared buffer, segments are received at input ports with each phase being shifted and are each composed of a predetermined length data in which each data is connected in series by a predetermined number. The segments are written in shared buffers at the same address in sequence for each segment, where the shared buffers are provided in parallel by the predetermined number. The address for each output port set in each segment is stored each time the writing is performed and the stored address is referred to in the sequence for each output port thereby to read each predetermined length data based on the address referred to from each shared buffer. Each predetermined length data read is connected in series and outputted to each output port. | 12-03-2009 |
| 20100232291 | DATA TRANSMISSION DEVICE - In a data transmission device and method provided with e.g. duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches are faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information. | 09-16-2010 |
| 20110096790 | SIGNAL PROCESSING CIRCUIT, INTERFACE UNIT, FRAME TRANSMISSION APPARATUS, AND SEGMENT DATA READING METHOD - A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer. | 04-28-2011 |
| 20110286468 | PACKET BUFFERING DEVICE AND PACKET DISCARDING METHOD - A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value. | 11-24-2011 |