Patent application number | Description | Published |
20090207850 | System and method for data packet transmission and reception - A system transmits a data packet from a transmitting apparatus to a receiving apparatus. The receiving apparatus includes a receive buffer, and a size specifying information transmitting unit that transmits size specifying information to the transmitting apparatus. The transmitting apparatus includes a transmit buffer, a credit storage unit that stores, as a credit, a value corresponding to a total size of all data packets stored in the receive buffer, a credit adding unit that adds a credit to the stored credit on transmitting a data packet, a credit subtracting unit that specifies a size of a read-out data packet on receiving the size specifying information, subtracts a credit corresponding to the specified size from a stored credit, and a transmission controlling unit that controls data packet transmission based on a credit stored in the credit storage unit. | 08-20-2009 |
20090300452 | ERROR IDENTIFYING METHOD, DATA PROCESSING DEVICE, AND SEMICONDUCTOR DEVICE - A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data. | 12-03-2009 |
20100067575 | DECODING METHOD, DECORDER AND DECODING APPARATUS - A decoding method generates a rectangular residual image by performing an inverse quantization and inverse frequency conversion processes based on coefficient data, a rectangular predicted image by reading a reference image based on motion vector data, and a decoded image by adding the residual image and the predicted image. The predicted images with respect to at least two or more rectangular regions are stored when generating the rectangular predicted image, and a predicted image ready signal notifies that the predicted image with respect to the at least two or more rectangular regions has been generated. The timings to store the coefficient data and the motion vector data are controlled in response to the predicted image ready signal. | 03-18-2010 |
20100275084 | TRANSMISSION DEVICE, RECEIVING CIRCUIT AND CONTROL METHOD OF TRANSMISSION DEVICE - A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period. | 10-28-2010 |
20110072296 | INFORMATION PROCESSING APPARATUS, DATA RECEPTION DEVICE AND METHOD OF CONTROLLING THE INFORMATION PROCESSING APPARATUS - A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value. | 03-24-2011 |
20110083059 | Information processing device, data transmitting device, and data transfer method of data transmitting device - A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated. | 04-07-2011 |
20110309868 | Data transfer unit, data transmission device, data receiving device, and control method - A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer. | 12-22-2011 |
20120008670 | SELF-TESTING APPARATUS AND METHOD FOR PHASE ADJUSTMENT CIRCUIT - A signal inversion unit inverts an adjustment pattern signal input as received data. A clock adjustment control circuit acquires a first TAP value adjusted and obtained when a phase adjusting operation is performed on a clock adjustment circuit in a state in which the adjustment pattern signal is not inverted, a first detection frequency of the adjustment pattern signal in a runtime of the operation, a second TAP value adjusted and obtained when the phase adjusting operation is performed in a state in which the adjustment pattern signal is inverted by the signal inversion unit, and a second detection frequency of the adjustment pattern signal in the runtime of the operation. A controller tests an operating state of the phase adjusting operation based on the first and second TAP values and the first and second detection frequencies of the adjustment pattern obtained by the clock adjustment control circuit. | 01-12-2012 |
20120239996 | MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING MEMORY CONTROLLER - A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data. | 09-20-2012 |