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Hiroshi Kanno

Hiroshi Kanno, Yokkaichi-Shi JP

Patent application numberDescriptionPublished
20110069532NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.03-24-2011
20110103128NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.05-05-2011
20110235400SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.09-29-2011

Hiroshi Kanno, Kodaira-Shi JP

Patent application numberDescriptionPublished
20110052937COPPER-ZINC ALLOY ELECTROPLATING BATH AND PLATING METHOD USING THE SAME - Disclosed is a cyanide-free copper-zinc alloy electroplating bath which can form a uniform and glossy plated layer having the desired composition in a large current density range, and a plating method using the same.03-03-2011

Hiroshi Kanno, Mie-Ken JP

Patent application numberDescriptionPublished
20110032745NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.02-10-2011

Hiroshi Kanno, Kawasaki-Shi JP

Patent application numberDescriptionPublished
20090327089MOBILE COMMUNICATION TERMINAL AND METHOD FOR ELECTRONIC MONEY SETTLEMENT - There is provided a settlement system comprising a mobile communication terminal, a settlement input device configured to output data of a charge, and a settlement device able to transfer money from a first account to a second account. The settlement input device comprises a first transmission unit configured to transmit the data of the charge to the mobile communication terminal, and a second transmission unit configured to transmit the data of the charge, identification data of the mobile communication terminal, and identification data of the settlement input device to the settlement device. The settlement device comprises a control unit configured to transfer an amount of money determined by the data of the charge from the first account to the second account, and a transmission unit configured to transmit the data of the amount of the transferred money to the mobile communication terminal. The mobile communication terminal comprises a first reception unit configured to receive the data of the charge from the settlement input device, a second reception unit configured to receive the data of the amount of the transferred money from the settlement device, and a display.12-31-2009
20100202186SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF SCREENING THE SAME - A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has a smaller width than widths of upper and lower portions of the diode.08-12-2010
20100213550NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si08-26-2010
20100237314RESISTANCE CHANGE TYPE MEMORY - A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.09-23-2010
20100237346NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer.09-23-2010
20110026299NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE/DATA ERASE THEREIN - A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit configured to control a voltage of selected one of the first lines, unselected ones of the first lines, selected one of the second lines, and unselected ones of the second lines, respectively. The variable resistor is configured to change its resistance value depending on a polarity of a voltage applied thereto. The voltage control circuit is configured to apply a voltage pulse to the selected one of the first lines and to connect a capacitor of a certain capacitance to one end of the selected one of the second lines.02-03-2011
20110210304STORAGE DEVICE - According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.09-01-2011

Patent applications by Hiroshi Kanno, Kawasaki-Shi JP

Hiroshi Kanno, Moriguchi City JP

Patent application numberDescriptionPublished
20110017261SOLAR CELL MODULE - In a solar cell module 01-27-2011

Hiroshi Kanno, Yokohama-Shi JP

Patent application numberDescriptionPublished
20090253618NEURONAL DIFFERENTIATION-INDUCING PEPTIDE AND USE THEREOF - A neuronal differentiation inducer comprising at least one peptide which can induce the differentiation of at least one cell into a neurocyte. The peptide is an artificially synthesized peptide comprising an amino acid sequence derived from a BC-box of at least one protein belonging to the SOCS protein family or an amino acid sequence having a partial modification in the BC-box-derived amino acid sequence, wherein the BC-box-derived amino acid sequence is composed of at least 10 contiguous amino acid residues selected in the amino acid sequence constituting the BC-box.10-08-2009
20100144034Method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells by introduction of Notch gene - There is provided a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells by introduction of a Notch gene. Specifically, the invention provides a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells in vitro, which method comprises introducing a Notch gene and/or a Notch signaling related gene into the cells, wherein the finally obtained differentiated cells are the result of cell division of the bone marrow stromal cells into which the Notch gene and/or Notch signaling related gene have been introduced. The invention also provides a method of inducing further differentiation of the differentiation-induced neural cells to dopaminergic neurons or acetylcholinergic neurons. The invention yet further provides a treatment method for neurodegenerative and skeletal muscle degenerative diseases which employs neural precursor cells, neural cells or skeletal muscle cells produced by the method of the invention.06-10-2010
20100310523Method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells by introduction of notch gene - There is provided a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells by introduction of a Notch gene. Specifically, the invention provides a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells in vitro, which method comprises introducing a Notch gene and/or a Notch signaling related gene into the cells, wherein the finally obtained differentiated cells are the result of cell division of the bone marrow stromal cells into which the Notch gene and/or Notch signaling related gene have been introduced. The invention also provides a method of inducing further differentiation of the differentiation-induced neural cells to dopaminergic neurons or acetylcholinergic neurons. The invention yet further provides a treatment method for neurodegenerative and skeletal muscle degenerative diseases which employs neural precursor cells, neural cells or skeletal muscle cells produced by the method of the invention.12-09-2010

Hiroshi Kanno, Tokyo JP

Patent application numberDescriptionPublished
20080269492Ionic Compound - The invention relates to novel ionic compounds with low risk of combustion, more particularly, ionic compounds represented by the general formula (I): (NPR10-30-2008
20090269502METHOD FOR PRODUCING CIRCULAR POLARIZATION SEPARATION SHEET, AND APPARATUS FOR COATING LAYER FORMATION - Provided are a method for producing a circular polarization separation sheet and an apparatus for coating layer formation, whereby a circular polarization separation sheet which selectively reflects a light in an entire visible light range is easily obtainable. A method for producing a circular polarization separation sheet including a step of obtaining on a substrate a photopolymerizable composition containing a liquid crystal compound, and a step of converting the coating layer into a resin layer having a cholesteric regularity, characterized in that the resin layer forming step includes: a selected ultraviolet light irradiation step (1) of irradiating the coating layer with a selected ultraviolet light having an illumination intensity of less than 10 mW/cm10-29-2009
20100304223NON-AQUEOUS ELECTROLYTE FOR BATTERY AND NON-AQUEOUS ELECTROLYTE BATTERY COMPRISING THE SAME AS WELL AS ELECTROLYTE FOR ELECTRIC DOUBLE LAYER CAPACITOR AND ELECTRIC DOUBLE LAYER CAPACITOR COMPRISING THE SAME - This invention relates to a safe electrolyte having no risk of igniting-firing, and more particularly to a non-aqueous electrolyte for a battery comprising an ionic liquid composed of a cation portion and an anion portion, and a supporting salt, characterized in that the cation portion of the ionic liquid contains phosphorus and nitrogen, as well as an electrolyte for an electric double layer capacitor comprising an ionic liquid composed of a cation portion and an anion portion, characterized in that the cation portion of the ionic liquid contains phosphorus and nitrogen.12-02-2010

Patent applications by Hiroshi Kanno, Tokyo JP

Hiroshi Kanno, Kawasaki JP

Patent application numberDescriptionPublished
20090018797Measuring method, measuring apparatus and computer readable information recording medium - A measuring apparatus has a walking determining part configured to determine a walking state of a to-be-measured person, a moving state determining part configured to determine a moving state in a specific direction of the to-be-measured person, a measurement result output determining part configured to determine whether or not measurement information concerning a movement of the to-be-measured person is to be output, based on a determination result of the walking state of the to-be-measured person by said walking determining part and a determination result of the moving state of the to-be-measured person by the moving state determining part.01-15-2009
20090318184Terminal device and method - A disclosed terminal device includes a detecting unit configured to detect whether the terminal device is held by a user; a judging unit configured to determine whether a predetermined condition is satisfied in the case where the terminal device is detected to be held; and an output unit configured to make a predetermined output in the case where the predetermined condition is determined to be satisfied.12-24-2009
20090325766EXERCISE CONDITION DETECTION APPARATUS, EXERCISE CONDITION DETECTION PROGRAM, AND EXERCISE CONDITION DETECTION METHOD - There is provided an exercise condition detection apparatus that detects a physical exercise condition. The exercise condition detection apparatus includes: an exercise intensity calculation section 12-31-2009
20100022352Walking exercise supporting device - A device can search for an appropriate walking route with an exercise condition such as of the calorie consumption and the walking speed. When a user enters information at least on the walking time, calorie consumption, walking speed, and distance as the exercise condition, the exercise condition is stored in a data storage unit of the device. When the user enters position information on the walking start point and the walking end point, the position information is also stored in the storage unit of the device. Map information is also previously stored in the data storage unit. A route searching unit of the device searches for the walking route and determines it according to the stored exercise condition, the position information and the map information. The determined walking route is presented to the user through a presenting unit of the device.01-28-2010
20100262899INFORMATION PROCESSING APPARATUS WITH TEXT DISPLAY FUNCTION, AND DATA ACQUISITION METHOD - A link processing unit links the music data and the lyric data acquired by a data acquiring unit with each other. If corresponding data is not present, the link processing unit causes the data acquiring unit to acquire the corresponding data and store it in a storage unit so as to link the music data with the lyric data. If a replay processing unit replays the music data, a synchronous display unit reads the corresponding lyric data and displays the lyrics in accordance with the progression of replay.10-14-2010
20100293464PORTABLE INFORMATION PROCESSING APPARATUS AND CONTENT REPLAYING METHOD - A portable information processing apparatus includes a replay processing unit that replays content data, a synchronous display unit that selects a piece of associated information corresponding to a replayed portion of the content data, and instructs to display the associated information thus selected, and an output controlling unit that displays the associated information that is selected by the synchronous display unit in an associated information display area arranged in a display unit. The synchronous display unit selects the associated information other than the one corresponding to the replayed portion and instructs the output controlling unit to display the information, upon accepting an operation requesting to display associated information other than the one corresponding to the replayed portion.11-18-2010

Patent applications by Hiroshi Kanno, Kawasaki JP

Hiroshi Kanno, Kobe-Shi JP

Patent application numberDescriptionPublished
20090032081SOLAR CELL MODULE AND METHOD FOR MANUFACTURING THE SAME - With the method for manufacturing the solar cell module according to the present embodiment, the width W02-05-2009
20100018563SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME - In the solar cell module 01-28-2010

Hiroshi Kanno, Osaka-Shi JP

Patent application numberDescriptionPublished
20080272859Photonic crystal device - A photonic crystal device according to the present invention includes: a first dielectric substrate 11-06-2008
20090274433PHOTONIC CRYSTAL DEVICE - A photonic crystal device according to the present invention includes: a first dielectric substrate 11-05-2009

Patent applications by Hiroshi Kanno, Osaka-Shi JP

Hiroshi Kanno, Kanagawa JP

Patent application numberDescriptionPublished
20090270334NEURONAL DIFFERENTIATION INHIBITOR PEPTIDE AND USE THEREOF - Disclosed is a neuronal differentiation inhibitor which comprises at least one peptide capable of inhibiting or controlling the neuronal differentiation of at least one cell capable of being differentiated into a neuronal cell. The peptide is an artificially synthesized peptide which comprises a BC-box derived amino acid sequence comprising at least 10 contiguous amino acid residues selected from an amino acid sequence constituting the BC-box of at least one protein belonging to the elongin A family or comprises an amino acid sequence having a partial modification in the BC-box derived amino acid sequence.10-29-2009

Patent applications by Hiroshi Kanno, Kanagawa JP

Hiroshi Kanno, Mie JP

Patent application numberDescriptionPublished
20110199811NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series of operations including an operation applying a first bias to the memory cell in a forward direction, and including an operation thereafter applying a second bias to the memory cell in a reverse direction; a storage unit storing an address of the defective memory cell; and an address control unit performing a control to avoid storing data in the defective memory cell whose address is stored in the storage unit.08-18-2011

Hiroshi Kanno, Hyogo JP

Patent application numberDescriptionPublished
20110247673SOLAR CELL MODULE - In a solar cell module 10-13-2011