| Patent application number | Description | Published |
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| 20090122467 | ELECTRIC DOUBLE-LAYER CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - In an electric double-layer capacitor, resistance of a polarizable electrode layer is reduced and gas generation inside a case is suppressed in an attempt to improve reliability. On that account, an electric double-layer capacitor is provided, which is obtained by housing in a case, together with a driving electrolyte, a capacitor element wound with a separator interposed between electrodes being paired anode and cathode electrodes in each of which polarizable electrode layers are formed on and lead wires are fixed to both sides of a current collector made of metallic foil, such that the polarizable electrode layers are opposed to each other. Further, an electric double-layer capacitor is provided in which the lead wire is fixed to a polarizable-electrode-layer-removed section on the electrode where the polarizable electrode layer has been removed, and an area of the polarizable-electrode-layer-removed section is not smaller than 1 and not larger than 2.0 when a project area of a portion where the lead wire is connected with the current collector is set to 1. | 05-14-2009 |
| 20090231781 | ELECTRIC DOUBLE LAYER CAPACITOR - An electric double layer capacitor includes a first collector, a first polarizable electrode layer provided on the first collector, a second collector, a second polarizable electrode layer provided on the second collector and facing the first polarizable electrode layer, a separator having an insulating property and provided between the first polarizable electrode layer and the second polarizable electrode layer, and a driving electrolyte impregnated in the first polarizable electrode layer and the second polarizable electrode layer. The polarizable electrode layers mainly contain activated carbon made from phenol resin, have a surface roughness not larger than 0.6 μm, and have an electrode density ranging from 0.5 g/cm | 09-17-2009 |
| 20090310281 | WOUND ELECTRIC DOUBLE-LAYER CAPACITOR - A wound electric double-layer capacitor suppresses electrochemical reaction on polarized electrode layers, reduces characteristic degradation, and has high reliability. The capacitor has a capacitor element formed by winding positive and negative electrodes with a separator interposed between them, a metal case for storing the capacitor element and an electrolyte for driving, and a sealing member for sealing an opening of the metal case. In the positive and negative electrodes, positive and negative electrode lead wires are coupled to exposed parts of current collectors having polarized electrode layers on their both surfaces, respectively. The negative electrode is wound at least one extra turn from the winding end of the positive electrode of the capacitor element, and hence a part where the polarized electrode layers formed in the negative electrode face each other through the separator is formed on the outermost periphery of the capacitor element. | 12-17-2009 |
| Patent application number | Description | Published |
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| 20090034314 | SEMICONDUCTOR MEMORY DEVICE - To secure a sufficient read-out voltage even when lines are arranged at a fine pitch, a semiconductor memory device including: a memory array in which a plurality of memory cells are arranged in rows and columns; and a plurality of bit lines associated with the respective columns of the memory cells is provided. The bit lines include main bit lines and sub bit lines to have a hierarchical structure, the main bit lines are divided among a plurality of interconnection layers, and a distance between the main bit lines in one of the interconnection layers is larger than a distance between the sub bit lines. | 02-05-2009 |
| 20090089646 | SEMICONDUCTOR STORAGE DEVICE - Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform. | 04-02-2009 |
| 20090135639 | SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, either two memory cell gates TG or a memory cell gate TG and a bit-line connecting gate SW are formed in every set of n-type doped regionsOOD at the intersections with word lines WL or bit-line selecting lines KS. A portion near the center of the set of n-type doped regions OD serves as a source/drain region shared by two gates, whereas portions near both ends thereof serve as source/drain regions for respective gates. Each of the source/drain regions is connected to a storage electrode SN of a memory cell capacitor via a storage contact CA or is connected to a sub bit line or a main bit line via a sub-bit-line contact CH and/or a via of a metal interconnection. A pattern formed of four memory cell gates TG and four bit-line connecting gates SW is repeated. | 05-28-2009 |
