| Patent application number | Description | Published |
|---|
| 20090059702 | Sense amplifier for semiconductor memory device - A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made. | 03-05-2009 |
| 20090201753 | Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address - There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit. | 08-13-2009 |
| 20090268542 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state. | 10-29-2009 |
| 20100034004 | SEMICONDUCTOR MEMORY DEVICE OF OPEN BIT LINE TYPE - There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat. | 02-11-2010 |
| 20100066406 | Semiconductor device - The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state. | 03-18-2010 |
| 20100109641 | Semiconductor device, internal circuit control signal measurement circuit, and delay time measurement method - In a semiconductor device manufactured in a semiconductor chip, an internal circuit generates first and second internal circuit control signals which are produced as a delay time measurement start signal and a delay time measurement stop signal, respectively, which are sent to a delay time measurement circuit. The delay time measurement circuit measures a delay time between the start and the stop signals and outputs the delay time. | 05-06-2010 |
| 20100110817 | Semiconductor device and refreshing method - A semiconductor device comprising a word line wired on a memory bank, a memory cell storing data provided in correspondence with the word line and a sense amplifier provided in correspondence with the word line, refreshing the memory cell corresponding to the word line selected by a row address that has been generated, including refresh counter | 05-06-2010 |
| 20100128548 | SEMICONDUCTOR DEVICE AND METHOD OF REFRESHING THE SAME - A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines. | 05-27-2010 |
| 20100142246 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region. | 06-10-2010 |
| 20110026290 | SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS - A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. | 02-03-2011 |
