Patent application number | Description | Published |
20120221679 | MICROCOMPUTER - Between a CPU and a communication module, a write buffer, a write control section, a read buffer and a read control section are provided. The CPU directly accesses and the write buffer and the read buffer. By periodically outputting a communication request, the read control section reads data, which the communication module received from other nodes, and transfers the data to the read buffer. The write control section transfers to the communication module the data written in the write buffer as transmission data. In addition, a bypass access control section and an access sequence control section are provided. The bypass access control section controls direct data read and data write between the CPU and the communication module. The access sequence control section controls sequence of accesses of the control sections to the communication module. | 08-30-2012 |
20120324320 | CODING APPARATUS, CODING METHOD, DATA COMMUNICATION APPARATUS, AND DATA COMMUNICATION METHOD - A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder. | 12-20-2012 |
20140105081 | COMMUNICATION NETWORK SYSTEM - In a communication network system with a plurality of nodes connected to a common transmission line, each master candidate node includes an idle time measurement device for measuring an idle time of the transmission line. Once each master candidate node acquires the master privilege and becomes a master node, the master node retains a master privilege until the idle time of the transmission line exceeds a longest of the privilege acquisition idle time widths of the master candidate nodes, the root node transmits a start frame indicating start of a next communicant cycle and the idle time measurement device is cleared upon receipt of the start frame. | 04-17-2014 |
20140177739 | TRANSMISSION DEVICE AND NODE FOR THE SAME - Nodes are connected in parallel between two transmission lines and configured to utilize a telecommunications standard of a differential transmission. At least one of the nodes includes two input/output terminals, a driver, a receiver, a resistor, and a comparator. The two input/output terminals are connected to the two transmission lines. The driver includes two output terminals connected to the two input/output terminals. The receiver includes two input terminals connected to the two input/output terminals. The resistor is connected between each of the two input/output terminals and one of a grand and a power supply voltage. The comparator compares a voltage between the transmission lines with a reference voltage to determine whether the transmission lines are in an idle state or in a communication state. | 06-26-2014 |
20140317380 | MULTI-CORE PROCESSOR - A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core. | 10-23-2014 |
20140344818 | TASK SCHEDULER, MICROPROCESSOR, AND TASK SCHEDULING METHOD - A task scheduler scheduling running units to execute a plurality of tasks is provided. The task scheduler includes a time control portion having a common time to control a state of the plurality of tasks, and a task calculator calculating a slack disappearance time for each of the plurality of tasks. An arrival time of one of the plurality of tasks is defined as T. A deadline time representing when the one of the plurality of tasks is required to be completed is defined as D. A worst case execution time predicted to be required for a completion of the one of the plurality of tasks is defined as W. A current elapsed time is defined as C. The slack disappearance time is expressed by S=T+D−W+C. A task having an earliest slack disappearance time from among the plurality of tasks is scheduled to be preferentially executed. | 11-20-2014 |
20140355724 | RECEIVING APPARATUS AND METHOD FOR DETECTING THE NUMBER OF BITS OF THE SAME VALUE IN A RECEIVED BIT STREAM - An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval. | 12-04-2014 |
20150019898 | DATA RECEPTION APPARATUS AND METHOD OF DETERMINING IDENTICAL-VALUE BIT LENGTH IN RECEIVED BIT STRING - A data reception apparatus calculates an integrated number of bits by integrating the number of bits in a received bit string; calculates an integrated number of samples by integrating the number of samples obtained by oversampling each bit; obtains a fitting line indicating correspondence between the integrated number of bits and the integrated number of samples based on a plurality of points of which each point corresponds to either only a rise edge or only a fall edge of each bit in the received bit string; and determines a bit length in the received bit string based on the fitting line. | 01-15-2015 |
20150063514 | DATA RECEPTION APPARATUS AND DATA COMMUNICATION SYSTEM - A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples). | 03-05-2015 |