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Hiroaki Ueno

Hiroaki Ueno, Osaka JP

Patent application numberDescriptionPublished
20090121775TRANSISTOR AND METHOD FOR OPERATING THE SAME - In a transistor, an AlN buffer layer 05-14-2009
20100090250SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.04-15-2010
20100097105SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a semiconductor layer stack 04-22-2010
20100237967CIRCUIT DEVICE - A circuit device includes a substrate 11, and a transmission line 09-23-2010
20100327320NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.12-30-2010
20110049574SEMICONDUCTOR DEVICE - A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.03-03-2011

Patent applications by Hiroaki Ueno, Osaka JP

Hiroaki Ueno, Tokyo JP

Patent application numberDescriptionPublished
20090146866WIRELESS APPARATUS, WIRELESS COMMUNICATION SYSTEM, CONTROL METHOD, AND CONTROL PROGRAM - A wireless apparatus which can realize a DFS function that avoidance of interference with radar is considered in an Ad-Hoc mode under a multihop circumstance is provided. A Beacon frame is transmitted at a shorter interval than a previously set interval when radar is detected by wireless apparatuses N06-11-2009
20100302671MAGNETIC RECORDING DEVICE, HEAD EVALUATION DEVICE, AND WRITE-POLE-ERASING EVALUATION METHOD - According to one embodiment, a magnetic recording device includes a write controller to control such that writing first information having a same polarity throughout the first information in a predetermined region including a plurality of tracks in a recording medium, writing second information in a target track located within or close to the predetermined region, and writing third information having, at an end of the writing, a polarity opposite to the polarity of the first information in a region of the target track in which the second information is not written, are performed; a read controller to control such that the second information is read after each of writing of the second information and writing of the third information; and a determiner to determine occurrence of pole erasing based on each second information read under the control by the read controller.12-02-2010
20110317301NONLINEARITY MEASUREMENT APPARATUS, NONLINEARITY MEASUREMENT METHOD, AND MAGNETIC RECORDING AND REPRODUCTION APPARATUS - According to one embodiment, a non-linearity measurement apparatus includes a first measurement module, a second measurement module, and a calculation module. The first measurement module is configured to measure a component of a first higher harmonic from a reproduced signal of a first signal recorded on a magnetic recording medium. The second measurement module is configured to measure a component of a second higher harmonic from a reproduced signal of a second signal recorded on the magnetic recording medium. The calculation module is configured to calculate a non-linear transition shift of the magnetic recording medium by calculating an arcsine function of a value obtained by dividing the component of the second higher harmonic by the component of the first higher harmonic.12-29-2011

Patent applications by Hiroaki Ueno, Tokyo JP

Hiroaki Ueno, Hachioji-Shi JP

Patent application numberDescriptionPublished
20100157461SIGNAL REPRODUCING CIRCUIT, MAGNETIC STORAGE DEVICE, AND SIGNAL REPRODUCING METHOD - According to one embodiment, a signal reproducing circuit reproduces a signal read from a recording medium on which the signal has been recorded by perpendicular magnetic recording. The signal reproducing circuit includes a waveform equalizer that equalizes the waveform of the signal based on a waveform equalization target, where D is a one-bit delay operator, previously stored in a storage module. The waveform equalization target is any one of a[1+3D+2D06-24-2010
20100238578METHOD FOR GENERATING WRITE CLOCK SIGNAL IN MAGNETIC DISK DRIVE - According to one embodiment, a write clock generator writes data to bits in a magnetic recording medium based on a write clock signal with a phase obtained by delaying the phase of a reference write clock signal. The write clock generator detects the amplitude of a read signal for the written data. The write clock generator repeats these operations with a phase delay varied. The write clock generator decides an optimum phase delay based on the amplitude detected for each phase delay.09-23-2010

Hiroaki Ueno, Wako-Shi JP

Patent application numberDescriptionPublished
20100123337VEHICULAR SIDE BODY STRUCTURE - Outer side sill member includes an upper wall section slanting upward in a horizontal, outer-to-inner direction, and a lower wall section slanting downward in the horizontal, outer-to-inner direction. At least one of upper and lower wall sections of the outer side sill member has a channel-shaped bead extending along the side sill, so that the side sill has a polygonal closed sectional shape extending in the front-rear direction of the vehicle. The bead has a bottom portion having a width greater than a vertical dimension in a direction orthogonal to the surface of the bottom portion. Each of bulkheads, partitioning the interior of the side sill, is fixedly joined to the outer side sill member with its recessed edge portion substantially fittingly engaging with the bottom portion of the depressed wall portion of the outer side sill member.05-20-2010

Hiroaki Ueno, Kawasaki JP

Patent application numberDescriptionPublished
20090086361STORAGE APPARATUS AND METHOD FOR PROCESSING RECORDING COMPENSATION - According to an aspect of an embodiment, a storage apparatus has a storage for storing a plurality of compensation values in association with a plurality of bit sequence patterns, a head for writing data into a medium and a controller for controlling the apparatus and driving the head, the controller determining whether to use one of the compensation values to drive the head to write an instantaneous data bit in dependence upon the immediate preceding data bits in reference to the bit sequence patterns.04-02-2009

Patent applications by Hiroaki Ueno, Kawasaki JP

Hiroaki Ueno, Sagamihara-Shi JP

Patent application numberDescriptionPublished
20120025770SECONDARY BATTERY PACK - A secondary battery pack of the present invention includes a secondary battery block 02-02-2012