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Hiroaki Niimi

Hiroaki Niimi, Dallas, TX US

Patent application numberDescriptionPublished
20090090990FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROVED NITROGEN DISTRIBUTION - Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.04-09-2009
20090159981STRAIN MODULATION IN ACTIVE AREAS BY CONTROLLED INCORPORATION OF NITROGEN AT Si-SiO2 INTERFACE - Adding nitrogen to the Si—SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been problematic due to loss of the nitrogen during liner oxide growth. This invention discloses a method of forming STI regions which have a controllable layer of nitrogen atoms at the STI sidewall interface. Nitridation is performed on the STI sidewalls by exposure to a nitrogen-containing plasma, by exposure to NH3 gas at high temperatures, or by deposition of a nitrogen-containing thin film. Nitrogen is maintained at a level of 1.0·1006-25-2009
20090166747FORMATION OF METAL GATE ELECTRODE USING RARE EARTH ALLOY INCORPORATED INTO MID GAP METAL - Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.07-02-2009
20100052071ENGINEERED OXYGEN PROFILE IN METAL GATE ELECTRODE AND NITRIDED HIGH-K GATE DIELECTRICS STRUCTURE FOR HIGH PERFORMANCE PMOS DEVICES - A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.03-04-2010
20100078738Method to Maximize Nitrogen Concentration at the Top Surface of Gate Dielectrics - An integrated circuit having a gate dielectric layer (04-01-2010
20100127335Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.05-27-2010
20100127336STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER - A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.05-27-2010

Patent applications by Hiroaki Niimi, Dallas, TX US

Hiroaki Niimi, Austin, TX US

Patent application numberDescriptionPublished
20080227266Method of STI corner rounding using nitridation and high temperature thermal processing - One embodiment of the present invention relates to a method of forming an isolation structure with rounded corners in a semiconductor substrate, comprising forming an isolation trench within the semiconductor substrate, performing an oxidation blocking nitridation process on exposed surfaces of the trench, performing corner rounding by oxidizing the exposed surfaces after the oxidation blocking nitridation process, and filling the trench with a dielectric material.09-18-2008
20080268603TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.10-30-2008
20080268627TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.10-30-2008

Hiroaki Niimi, Tokyo JP

Patent application numberDescriptionPublished
20110120374System and Method for Mitigating Oxide Growth in a Gate Dielectric - Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.05-26-2011

Patent applications by Hiroaki Niimi, Tokyo JP