Patent application number | Description | Published |
20080243470 | LOGICAL CHECK ASSIST PROGRAM, RECORDING MEDIUM ON WHICH THE PROGRAM IS RECORDED, LOGICAL CHECK ASSIST APPARATUS, AND LOGICAL CHECK ASSIST METHOD - A computer-readable medium stores a program which, when executed by a computer, causes the computer to execute functions including an extraction operation of extracting a sequence of character strings that are arranged in order of transitions and indicate meanings of transition conditions of transition branches that are taken to reach each transition state starting from an initial state from a finite state machine model of a hardware module which is a check subject; a generation operation of generating message information which means transitions that are taken to reach each transition state starting from the initial state by burying the sequence of character strings extracted by the extraction operation at a burying position for a partial character string which is part of a character string indicating each state of the finite state machine model; and an output operation of outputting the message information generated by the generation operation. | 10-02-2008 |
20080312890 | SPECIFICATION VERIFICATION PROGRAM, COMPUTER-READABLE STORAGE MEDIUM STORING SPECIFICATION VERIFICATION PROGRAM, SPECIFICATION VERIFICATION APPARATUS, AND SPECIFICATION VERIFICATION METHOD - Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output. | 12-18-2008 |
20100106477 | MEDIUM STORING LOGIC SIMULATION PROGRAM, LOGIC SIMULATION APPARATUS, AND LOGIC SIMULATION METHOD - A logic simulation apparatus includes: a jitter detector generation section | 04-29-2010 |
20100194436 | VERIFICATION SUPPORT SYSTEM AND METHOD - A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic. | 08-05-2010 |
20110161903 | VERIFICATION SUPPORT COMPUTER PRODUCT AND APPARATUS - A computer-readable, non-transitory medium stores therein a verification support program that causes a computer to execute first detecting a state change in a circuit and occurring when input data is given to the circuit; second detecting a state change in the circuit and occurring when the input data partially altered is given to the circuit; determining whether a difference exists between a series of state changes detected at the first detecting and a series of state changes detected at the second detecting; and outputting a determination result obtained at the determining. | 06-30-2011 |
20110205903 | MONITORING APPARATUS, METHOD, AND COMPUTER PRODUCT - A non-transitory computer-readable recording medium stores therein a monitoring program that causes a computer monitoring data transmission from a transmission source device to a transmission destination device to execute a process that includes detecting data transmitted in a sequence that differs from a specified sequence; determining whether the sequence that differs is permissible by a specified constraint, if data transmitted at the sequence that differs is detected at the detecting; and outputting a determination result obtained at the determining. | 08-25-2011 |
20120005335 | Computer product , verification support apparatus, and verification support method - A computer-readable, non-transitory medium storing therein a verification support program that causes a computer to execute a process that includes detecting a point in time when data of any one transaction among a series of transactions that are to be transmitted in a prescribed sequence from a device under verification, is skipped; detecting a point in time when the data is first transmitted after the detected point in time when the data is skipped; computing time elapsing from the detected point in time when the data is skipped until the detected point in time when the data is transmitted; and outputting a computation result obtained at the computing. | 01-05-2012 |
20120005545 | Computer product, verification support apparatus, and verification support method - A computer-readable, non-transitory medium stores a program that causes a computer to execute detecting in a circuit-under-test, a change in a signal output from each circuit element on a transmission-side, during one clock cycle on a reception-side at an asynchronous location; inputting to each circuit element on the reception-side, a signal for which a change is not detected at a detection time among detection times when a signal change is detected at the detecting and replacing with a random logic value, a signal for which a change has been detected at a detection time among the detection times and inputting the random logic value to each circuit element on the reception-side, in an action triggered by a rising edge of an operation clock on the reception-side after the one clock cycle; and outputting for each circuit element on the reception-side, an operation result obtained based on input at the inputting. | 01-05-2012 |
20120209583 | COMPUTER PRODUCT, VERIFICATION SUPPORT APPARATUS, AND VERIFICATION SUPPORT METHOD - A computer-readable medium stores therein a verification support program that causes a computer to execute a process including first detecting an assertion that evaluates to true during simulation of a circuit, the assertion being detected from an assertion group prescribing values of registers to be met by the circuit; updating, at a clock tick subsequent to a clock tick at which the assertion is detected at the first detecting, an expected value of a register, to a value of the register as prescribed by the assertion; second detecting inconsistency between the expected value that has been updated at the updating and the value of the register; determining, based on a detection result obtained at the second detecting, validity of a change in the value of the register; and outputting a determination result obtained at the determining. | 08-16-2012 |
20120210282 | VERIFICATION SUPPORT APPARATUS, VERIFYING APPARATUS, COMPUTER PRODUCT, VERIFICATION SUPPORT METHOD, AND VERIFYING METHOD - A verification support apparatus includes a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive a signal in a second clock domain that receives the signal from a first clock domain asynchronously; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit. | 08-16-2012 |
20120239328 | WAVEFORM ANALYZER AND WAVEFORM ANALYSIS METHOD - A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions. | 09-20-2012 |