| Patent application number | Description | Published |
|---|
| 20090045526 | Stacked memory without unbalanced temperature distributions - A stacked memory without unbalanced temperature distributions is disclosed. According to one aspect of the invention, a through electrode in each layer is connected one after the other such that regions to be activated in neighboring layers do not overlap in a vertical direction. According to another aspect of the invention, each layer comprises an activation region distribution circuit for outputting an activation signal to, among the regions of the layer, a region having an address different from an address of a region to be activated in a layer adjacent to the layer in question. | 02-19-2009 |
| 20090109641 | Wafer of circuit board and joining structure of wafer or circuit board - A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion | 04-30-2009 |
| 20090134498 | SEMICONDUCTOR APPARATUS - The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material. | 05-28-2009 |
| 20090219745 | MEMORY MODULE AND MEMORY DEVICE - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 09-03-2009 |
| 20090220025 | Transmission method, transmission circuit and transmission system - A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data. | 09-03-2009 |
| 20090294990 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 12-03-2009 |
| 20090315147 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film. | 12-24-2009 |
| 20090315872 | LIQUID CRYSTAL DISPLAY APPARATUS AND LIQUID CRYSTAL PANEL DRIVING MEHTOD - A liquid crystal display apparatus includes common voltage generator circuit ( | 12-24-2009 |
| 20100193962 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 08-05-2010 |
| 20100232201 | STACKED SEMICONDUCTOR MEMORY DEVICE - A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes. | 09-16-2010 |
| 20110059229 | METHOD OF MANUFACTURING GLASS SUBSTRATE AND INFORMATION RECORDING MEDIUM - In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method. | 03-10-2011 |
| 20110104852 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 05-05-2011 |
| 20110141789 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 06-16-2011 |
