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Hirashiki
Allen A. Hirashiki, San Ramon, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110116233 | Fan Tray that is Installable and Removable from the Front and Back of a Network Element Chassis - A fan tray for a network element that is installable and removable from the front and back of a network element. The fan tray includes one or more fans in a housing to provide cooling for the network element, an engagement rod with ends that protrude out a front and back of the housing, a first engagement lever at one end of the engagement rod and a second engagement lever at an opposite end of the engagement rod, the first and second engagement levers are movable between an unlocked and locked position and movement is tied together, a gearing mechanism coupled to the engagement rod to translate rotational force applied to the engagement levers into linear force to extend and withdraw a backplane connector assembly coupled to the gearing mechanism. The backplane connector assembly includes a backplane connector to engage and disengage with a fan tray connector of a backplane of the network element in a plane perpendicular to the installation plane of the fan tray according to movement of the engagement levers responsive to the engagement levers respectively moving to the locked and unlocked position. | 05-19-2011 |
Kenichi Hirashiki, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110050354 | VOLTAGE CONTROL OSCILLATOR AND QUADRATURE MODULATOR - A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor. | 03-03-2011 |
| 20110234311 | CURRENT DETECTION CIRCUIT AND INFORMATION TERMINAL - According to one embodiment, a current detection circuit is provided with: a NMOS transistor, whose control signal is given to a gate electrode, whose source electrode is connected to a ground line, and whose drain electrode is connected to an input/output terminal; a first PMOS transistor, in which the control signal is given to a gate electrode, and whose drain electrode is connected to the input/output terminal and the drain electrode of the NMOS transistor; and a second PMOS transistor, whose drain electrode is connected to the source electrode of the first PMOS transistor, and a first supply voltage is given to a source electrode. A detection section detects whether or not a current has changed at the input/output terminal from a change in current flowing through the second PMOS transistor. | 09-29-2011 |
Kenichi Hirashiki, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20110304387 | CURRENT MIRROR CIRCUIT - In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs. | 12-15-2011 |