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Hiraide, JP
Akiyuki Hiraide, Yokosuka-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100120641 | POUR POINT DEPRESSANT FOR LUBRICANT - There is provided a pour point depressant for lubricants that has an effect of lowering pour points of both solvent refined base oils and high viscosity index base oils. A pour point depressant for lubricants comprising: a mixture of an alkyl(meth)acrylate polymer (A) that is composed of an alkyl(meth)acrylate containing alkyl groups having an average carbon number (C | 05-13-2010 |
Fumio Hiraide, Ebina-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100033598 | Information input apparatus and method - An electronic camera is capable of recording image, voice, text, line-drawn information and the like. A release switch in the electronic camera is operated to photograph a subject image. When recording voice with the electronic camera, shutter sound effects are not output with the recorded voice. Further, the photographic operation can be indicated to the user by lighting a light-emitting diode in a finder when the release switch is operated. | 02-11-2010 |
| 20110128409 | Information input apparatus and method - An electronic camera is capable of recording image, voice, text, line-drawn information and the like. A release switch in the electronic camera is operated to photograph a subject image. When recording voice with the electronic camera, shutter sound effects are not output with the recorded voice. Further, the photographic operation can be indicated to the user by lighting a light-emitting diode in a finder when the release switch is operated. | 06-02-2011 |
Hiroaki Hiraide, Nagoya-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110242217 | LIQUID EJECTION HEAD AND METHOD OF MANUFACTURING THE SAME - A liquid ejection head including: a base plate member having ejection holes and an ejection face having ejection openings; and an actuator; wherein the ejection face has first and second recessed portions extending in one direction and arranged in a perpendicular direction, wherein the ejection openings are formed in bottom portions of the respective first recessed portions; wherein each second recessed portion and a corresponding first recessed portion are arranged side by side such that a separation distance therebetween is not smaller than a separation distance between two first recessed portions located side by side at the shortest distance among first recessed portions and is shorter than a separation distance between two first recessed portions located side by side at the greatest distance among the first recessed portions; and wherein on the bottom portions is formed a liquid repellent layer having not been removed due to a masking material having entered into the first recessed portions to cover the liquid repellent layer. | 10-06-2011 |
Junji Hiraide, Chiba JP
| Patent application number | Description | Published |
|---|---|---|
| 20090121876 | Ic Tag Whose Function Can Be Changed Upon Separation - Data falsification or the like is prevented and security is enhanced in an IC tag. The IC tag consists of three portions: separable portions A | 05-14-2009 |
Keisuke Hiraide, Aichi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100088813 | AIR SUCTION DEVICE FOR TOILET DRAINAGE CHANNEL - An air suction device for a toilet drainage channel, capable of good and silent toilet flushing. The air suction device ( | 04-15-2010 |
Mamoru Hiraide, Saitama JP
| Patent application number | Description | Published |
|---|---|---|
| 20110158103 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a test module section that tests the device under test; a test control section that generates control packets for controlling the test module section; and a connecting section that receives the control packets from the test control section and transmits the control packets to the test module section. The test module section includes a first test module that operates according to control packets having a first packet structure and a second test module that operates according to control packets having a second packet structure, which is obtained by adding an expansion region to a control packet having the first packet structure, the test control section transmits control packets having the second packet structure to the connecting section, and the connecting section (i) removes the expansion region from control packets having the second packet structure received from the test control section and transmits the resulting control packets to the first test module, and (ii) transmits control packets having the second packet structure received from the test control section to the second test module. | 06-30-2011 |
| 20110161041 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising: a test module that tests the device under test by sending signals to and receiving signals from the device under test; a test controller that controls the test module; and a network that transmits communication packets between the test module and the test controller, wherein at least one of the test module and the network transmits to the test controller a usage state packet that indicates a usage state of a communication buffer that buffers the communication packets. | 06-30-2011 |
| 20110181310 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus for testing a device under test, including: a plurality of test modules that exchange signals with the device under test; a bus to which the plurality of test modules are connected; and a test control section that controls the plurality of test modules via the bus, where each of the plurality of test modules includes: a test section that exchanges signals with the device under test, and a module control section that controls the test section, and the module control section of each test module exchanges signals with the module control section of another test module, via the bus. | 07-28-2011 |
| 20110181311 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus and a test method related to the test apparatus for testing a device under test, including: a plurality of test modules that exchange a signal with the device under test; a test control section that outputs a group read instruction for collectively reading data stored in two or more of the test modules; and a control interface section that reads the data from the two or more test modules according to the group read instruction, and collectively sends the read data to the test control section. | 07-28-2011 |
| 20110184687 | TEST APPARATUS AND TEST METHOD - A test apparatus for testing a device under test includes a test module that exchanges signals with the device under test to test the device under test, a test controller that includes a processor and a memory, where the test controller controls the test module, and a network that transfers communication packets between the test module and the test controller. Here, the test controller includes a receiving section that receives an interrupt packet requesting an interrupt to the test controller, from the test module via the network, a memory writing section that writes interrupt information included in the interrupt packet into the memory, and an interrupt notifying section that notifies the processor of the interrupt to cause the processor to reference the interrupt information written into the memory. | 07-28-2011 |
Nobuhiko Hiraide, Hiraki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100272594 | FERRITIC STAINLESS STEEL WITH EXCELLENT BRAZEABILITY - This ferritic stainless steel with excellent brazeability includes, in terms of mass percent, 0.03% or less of C, 0.05% or less of N, 0.015% or more of C+N, 0.02 to 1.5% of Si, 0.02 to 2% of Mn, 10 to 22% of Cr, 0.03 to 1% of Nb, and 0.5% or less of Al, and further includes Ti in a content that satisfies the following formulae (1) and (2), with the remainder composed of Fe and unavoidable impurities. | 10-28-2010 |
Nobuhiko Hiraide, Shuunan-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100150770 | Stainless Steel Excellent in Corrosion Resistance, Ferritic Stainless Steel Excellent in Resistance to Crevice Corrosion and Formability, and Ferritic Stainless Stee Excellent in Resistance to Crevice Corrosion - The stainless steel of the first embodiment includes C: 0.001 to 0.02%, N: 0.001 to 0.02%, Si: 0.01 to 0.5%, Mn: 0.05 to 0.5%, P: 0.04% or less, S: 0.01% or less, Ni: more than 3% to 5%, Cr: 11 to 26%, and either one or both of Ti: 0.01 to 0.5% and Nb: 0.02 to 0.6%, and contains as the remainder, Fe and unavoidable impurities. The stainless steel of the second embodiment has an alloy composition different from those of the first and third embodiments and satisfies the formula (A): Cr+3Mo+6Ni≧23 and formula (B): Al/Nb≧10 and contains as the remainder, Fe and unavoidable impurities. The stainless steel of the third embodiment has an alloy composition different from those of the first and second embodiments and includes either one or both of Sn: 0.005 to 2% and Sb: 0.005 to 1% and contains as the remainder, Fe and unavoidable impurities. | 06-17-2010 |
Nobulhiko Hiraide, Shunan-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110110812 | FERRITE STAINLESS STEEL FOR USE IN PRODUCING UREA WATER TANK - This ferrite stainless steel for use in producing a urea water tank includes: in terms of mass %, C: 0.05% or less; N: 0.05% or less; Si: 0.02 to 1.5%; Mn: 0.02 to 2%; Cr: 15 to 23%; and either one or both of Nb and Ti at a content within a range of 8(C+N) to 1% (herein, C and N represent the contents of C and N (expressed by mass %), respectively, and the numerical values shown in front of the atomic symbols represent constant numbers), with the remainder being iron and unavoidable impurities, wherein an effective amount of Cr expressed by any one of the following Equations (I), (II), and (III) is 15% or more (herein, the atomic symbols in Equations (I) to (III) represent the contents of the elements (expressed by mass %), and the numerical values shown in front of the atomic symbols represent constant numbers). Here, the effective amount of Cr=Cr+4Si−2Mn in the case where only Nb is contained, the effective amount of Cr=Cr+4Si−2Mn−10Ti in the case where only Ti is contained, and the effective amount of Cr=Cr+4Si−2Mn−(10Ti−3Nb) in the case where both of Nb and Ti are contained. | 05-12-2011 |
Noriaki Hiraide, Shiojiri-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090321979 | METHOD AND DEVICE FOR FORMING THREE-DIMENSIONAL MODEL, SHEET MATERIAL PROCESSING METHOD, AND SHEET MATERIAL PROCESSING DEVICE - Three-dimensional models can be produced by a sheet deposition method using a sheet material made of water-soluble paper as the depositing material. Each layer of the sheet material is made severable along the contour lines of the three-dimensional model by discharging water using the nozzle of a fluid discharge head onto each layer of the sheet material. A coloring solution is discharged from the fluid discharge head when each layer is deposited to color the sheet material. After the deposition is completed, the unnecessary parts of the sheet material can be pulled away to complete the three-dimensional model. Alternatively, by discharging a setting solution using a nozzle of the fluid discharge head onto each layer of the sheet material, each layer of the sheet material in the section area of the three-dimensional model can be insolubilized, and a color setting solution can be discharged to color and set the colored parts. After the deposition is completed, the deposition can be immersed in water to remove the sheet material that was not insolubilized and complete the three-dimensional model. | 12-31-2009 |
Takahisa Hiraide, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080222474 | Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product - In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log | 09-11-2008 |
Takahisa Hiraide, Shinjuku JP
| Patent application number | Description | Published |
|---|---|---|
| 20090245001 | INTEGRATED CIRCUIT AND METHOD FOR TESTING THE CIRCUIT - An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated. | 10-01-2009 |
Takahisa Hiraide, Yokohama JP
| Patent application number | Description | Published |
|---|---|---|
| 20130039114 | WRITING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND WRITING METHOD - A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch. | 02-14-2013 |
Toshinori Hiraide, Fujimi-Machi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110187769 | RECORDING APPARATUS - A recording apparatus that records onto recording paper includes: a main case housing a noise source that generates noise when printing is carried out; a scanner space portion that is within the main case but that is independently separate from a housing space portion of the noise source; and a communication tube portion that communicates between the housing space portion and the scanner space portion. An inner surface area that intersects with the axial direction of the communication tube portion at the inner surface of the scanner space portion is formed of a document platform glass whose surface density is higher than that of the material of which the other wall surface areas are formed in the inner surface of the scanner space portion. | 08-04-2011 |