Hioka
Eiichi Hioka, Toyota-Shi JP
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20100270963 | MALFUNCTION DETERMINATION DEVICE FOR MOTOR CONTROL SYSTEM - A malfunction determination device for a motor control system, outputs a position signal that indicates a moved position of a movable member of a motor and a direction signal that indicates a movement direction of the movable member. The malfunction determination device determines a malfunction has occurred if a relationship between the position signal and the direction signal differs from that when the motor control system is operating normally. The malfunction determination device outputs a pulse signal that varies periodically along with variations in the moved position of the movable member as the position signal; outputs a periodic pulse signal in the same phase with the position signal as the direction signal if the movable member is moving in one direction; and outputs a periodic pulse signal in an opposite phase to the position signal as the direction signal if the movable member is moving in the other direction. | 10-28-2010 |
20130092111 | CONTROL DEVICE OF ACTUATOR - An electronic control unit ( | 04-18-2013 |
Eiichi Hioka, Aichi-Ken JP
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20100106355 | CONTROL UNIT AND CONTROL METHOD FOR VARIABLE VALVE TIMING MECHANISM, PROGRAM FOR IMPLEMENTING THE CONTROL METHOD, AND RECORDING MEDIUM ON WHICH THE PROGRAM IS RECORDED - An ECU executes a program based on which, when a fuel-supply cutoff control is executed or when a hybrid vehicle travels in a second mode in which the engine is stopped and the hybrid vehicle travels using only the drive power generated by a second MG an intake VVT mechanism is controlled so that a valve phase is brought to the mechanically determined most retarded phase. The phase, which is detected by a cam position sensor, is learned as the most retarded phase. | 04-29-2010 |
Katsuya Hioka, Tokyo JP
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20110241674 | Sample Tube and Measurement Method for Solid-State NMR - A solid-state NMR sample tube and method of using same which can be spun stably and at high speed while suppressing its bending resonance. A solid sample to be investigated by solid-state NMR spectroscopy can be sealed in the sample tube. The sample tube includes a hollow cylinder having opposite ends. At least one of the ends is open. The sample tube has a length L, an outside diameter D, and an inside diameter d which satisfy a given relationship disclosed herein. | 10-06-2011 |
20130207656 | NMR Probe - An NMR probe has a sample tube insertion port for introducing and withdrawing the sample tube into and from the probe, a sample tube support providing support of the sample tube during NMR measurements, a tubular sample tube passage connecting together the sample tube insertion port and the sample tube support and capable of transporting the sample tube between them, and a gas stream generator for producing a gas stream in the sample tube passage to move the sample tube between the sample tube insertion port and the tube support. The gas stream generator is mounted at an intermediate (non-end) position in the sample tube passage. | 08-15-2013 |
Takaaki Hioka, Chiba-Shi JP
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20120001279 | Hall sensor - Provided is a highly-sensitive Hall element capable of eliminating an offset voltage without increasing the chip size. At the four vertices of a square Hall sensing portion, Hall voltage output terminals and control current input terminals are respectively arranged independently from each other. The Hall voltage output terminals all have the same shape. The control current input terminals are arranged on both sides of the Hall voltage output terminals, respectively, to be spaced apart from the Hall voltage output terminals so as to prevent electrical connection to the Hall voltage output terminals, and have the same shape at the four vertices. | 01-05-2012 |
20120001280 | Hall sensor - Provided is a highly-sensitive Hall element capable of eliminating an offset voltage without increasing the chip size. The Hall element includes: a Hall sensing portion having a shape of a cross and four convex portions; Hall voltage output terminals which are arranged at the centers of the front edges of the four convex portions, respectively; and control current input terminals which are arranged on side surfaces of each of the convex portions independently of the Hall voltage output terminals. In this case, the Hall voltage output terminal has a small width and the control current input terminal has a large width. | 01-05-2012 |
Takehiko Hioka, Ritto-Shi JP
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20090024230 | PROGRAM DEVELOPMENT SUPPORT APPARATUS OF SAFETY CONTROLLER - The arrangement of the function block to the programming field is performed according to the guide by a function block arrangement template in which block arrangeable positions are defined vertically and horizontally and in which one end side in a row direction is defined as an input terminal side and the other end side is defined as an output terminal side; and the template is separated into an input side template positioned on an input side and including a series of plural columns respectively accepting the arrangement of a predetermined type of function block related to an input signal, and an output side template positioned on an output side and including a series of plural columns respectively accepting the arrangement of a predetermined type of function block related to an output signal. | 01-22-2009 |
20090171472 | SAFETY MASTER - A safety master configured to communicate with a plurality of safety slaves over a safety field network or with a plurality of safety local I/O units connected by a safety back plane bus of the safety master, wherein each of the plurality of safety slaves and safety local I/O units allow connection to safety I/O devices in a plurality of cell equipment, and wherein the safety master receives a status signal indicating a “safe state” or an “unsafe state” related to cell equipment from each of the corresponding plurality of safety slaves or safety local I/O units, and controls operation/stop of cell equipment by executing an interlock operation program with the received status signal as an input to output an operation instruction signal. | 07-02-2009 |
Takeshi Hioka, Kanagawa-Ken JP
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20130258796 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a stacked layer memory block and associated peripheral circuits in stacked layer arrangements. Booster circuits in a variety of stacked layer arrangements are described. The booster circuit possesses plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive the first clock signal on one end, and the other ends are each connected to one end of different rectifier cells. The first capacitor is composed of capacities between plural first conductive layers that are arrayed with a set pitch perpendicularly to the substrate. One of the either even numbered or odd numbered first conductive layers is supplied with a first clock signal. The other of the either even numbered or odd numbered first conductive layers that line perpendicularly to the substrate is, individually, connected to one end of different rectifier cells. | 10-03-2013 |
Takeshi Hioka, Kawasaki-Shi JP
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20100237933 | CURRENT SUPPLY CIRCUIT - A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal. | 09-23-2010 |
Takeshi Hioka, Yokohama-Shi JP
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20110234306 | BOOSTER CIRCUIT - In a booster, a first transistor of a second conduction-type is formed on a first conduction-type substrate and connected to between a voltage-source and an output so that the first transistor functions as a diode. A first capacitor is connected to a first node of the first transistor on a voltage-source side, and transmits a first clock to the first node. A second transistor of the first conduction-type is connected to a second node of the first transistor on an output side to receive the first clock. A second capacitor is connected to the second node and transmits a second clock having an opposite phase of the first clock to the second node. The first transistor transfers the first node's voltage stepped up by the first clock to the second node. The second transistor transfers the second node's voltage stepped up by the second clock to an output side. | 09-29-2011 |
20120068763 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level. | 03-22-2012 |
20130128673 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells storing data based on respective threshold voltages, having a positive threshold voltage in a data erased state, and includes respective control electrodes. Word lines are selectively electrically connected to the control electrodes of the memory cells, and charged to a potential before writing data to the memory cells. A voltage generator outputs a voltage at an output and includes a first path which discharges the output. A connection circuit is selectively electrically connected to the output of the voltage generator and a first word line, and selectively electrically connects the first word line to a first node which supplies a potential. | 05-23-2013 |
20130134957 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit according to one embodiment includes a first booster circuit configured to generate a first voltage having a first voltage value, and a second booster circuit group including a plurality of second booster circuits, each second booster circuit configured to generate a second voltage having a second voltage value. The second booster circuits switch to be connected in series and are configured to be capable of generating the first voltage together with the first booster circuit in a change from a first state to a second state. | 05-30-2013 |
20130242651 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second conductive layers function as a second electrode of the first capacitor. The first conductive layers and the second conductive layers are arranged alternately in the direction substantially perpendicular to a semiconductor substrate. A control circuit is configured to control a voltage applied to each of first conductive layers and the second conductive layers according to voltages of gates of a plurality of memory transistors, thereby changing a capacitance of the first capacitor. | 09-19-2013 |
20140070295 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a capacitor. | 03-13-2014 |
Takeshi Hioka, Kanagawa JP
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20130113080 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode. | 05-09-2013 |
20130301354 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells and a voltage generating circuit for generating a voltage for memory cells. The first voltage generating circuit includes a first diode connected between first and second nodes, a first transistor connected between the output terminal and a third node and having a gate connected to the second node, a second transistor connected between the third node and a fourth node and having a gate connected to the second node, a third transistor connected between the output terminal and the first node and having a gate connected to the fourth node, a second diode connected between the first and fourth nodes, and a charge pump circuit configured to supply a voltage to the fourth node. The first voltage generating circuit functions to adjust the generated voltage when it overshoots a desired value which may be caused by capacitive coupling with adjacent wirings. | 11-14-2013 |