Patent application number | Description | Published |
20100220536 | ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE - A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock. | 09-02-2010 |
20130128682 | MEMORY SYSTEM WITH DYNAMIC REFRESHING - An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic. | 05-23-2013 |
20140223117 | SECURING THE CONTENTS OF A MEMORY DRIVE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140281202 | DRAM CONTROLLER FOR VARIABLE REFRESH OPERATION TIMING - A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing. | 09-18-2014 |
20140359197 | IMPLEMENTING REINFORCEMENT LEARNING BASED FLASH CONTROL - A method and system are provided for implementing enhanced flash storage control using reinforcement learning to provide enhanced performance metrics. A flash controller, such as a Reinforcement Learning (RL) flash controller, is coupled to a flash storage. The flash controller defines a feature set of flash parameters determined by a predefined one of a plurality of optimization metrics. The optimization metric is adapted dynamically based upon system workload and system state. The flash controller employing the feature set including at least one feature responsive to erase operations; computes a current system state responsive to the employed feature set; selects actions at each time step by sensing the computed current system state for performing an action to maximize a long term reward, and moves to another state in the system while obtaining a short-term reward for the performed action. | 12-04-2014 |
20150032968 | IMPLEMENTING SELECTIVE CACHE INJECTION - A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element. | 01-29-2015 |
20150074356 | PROCESSOR WITH MEMORY-EMBEDDED PIPELINE FOR TABLE-DRIVEN COMPUTATION - A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction. | 03-12-2015 |
20150074381 | PROCESSOR WITH MEMORY-EMBEDDED PIPELINE FOR TABLE-DRIVEN COMPUTATION - A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction. | 03-12-2015 |