Patent application number | Description | Published |
20090009292 | RFID INTERROGATOR - Embodiments of the invention relate to the field of RFID interrogators, particularly RFID interrogators that combine low loss with high rates of communication from the interrogator to a tag. We describe a transmitter comprising a resonant circuit and a driver coupled to drive said resonant circuit, wherein said resonant circuit includes a resonance regeneration system such that during amplitude modulation of a resonant signal in said resonant circuit when an amplitude of said resonant signal is reduced energy from said reduction is stored and when said amplitude is increased said stored energy is used to regenerate said resonance signal. | 01-08-2009 |
20100097187 | RFID TAGS - We describe RFID tags that incorporate a nonlinear resonator that self-adapts to the driving frequency of a reader. More particularly we describe an RF tag for sending data to a tag reader by modulating energy drawn from an RF field of said tag reader, the tag comprising: an antenna; a resonant circuit coupled to said antenna to resonate at a frequency of said RF field; a local power store to store power extracted from said RF field; a modulation system to modulate one or both of the resonance amplitude and a relative phase of a signal in said resonant circuit with respect to said RF field; and a feedback circuit coupled to said resonant circuit and to said local power store to control one or both of said resonance amplitude and said relative phase to control transients in said resonance amplitude caused by said modulation. | 04-22-2010 |
20100102932 | RFID TRANSMITTER - Embodiments of the invention relate to the field of RFID interrogators, particularly RFID interrogators that combine low loss with high rates of communication from the interrogator to a tag. Further embodiments relate to the field of active RFID tags and general radio transmitters. We describe a transmitter comprising a resonant circuit and a driver coupled to drive said resonant circuit, wherein said resonant circuit includes a resonance regeneration system such that during amplitude modulation of a resonant signal in said resonant circuit when an amplitude of said resonant signal is reduced energy from said reduction is stored and when said amplitude is increased said stored energy is used to regenerate said resonance signal. | 04-29-2010 |
20100289617 | RFID Reader - Embodiments of the invention relate to the field of RFED (radio frequency identification). Some particularly preferred embodiments relate to a high-Q, so-called “full duplex” (FDX) RFID Reader. An RFID tag reader, the reader comprising: an electromagnetic (em) field generator for generating an electromagnetic (em) field for modulation by said tag, said modulation comprising modulated load of said em field by said tag; a detector system responsive to fluctuations in strength of said em field at said reader; a negative feedback system responsive to said detector system to provide a control signal for said em field generator for controlling said em field generator to reduce said detected fluctuations; and a demodulator responsive to said control of said em field to demodulate said em field modulation by said tag. | 11-18-2010 |
20100328030 | RFID PET DOOR - An RFID reader for use in a pet door to control access for a pet bearing an RFID tag or implant. The RFID reader incorporates and is operable in two modes, a learn mode and a normal mode. In learn mode, the reader stores the ID code of an RFID transponder in the vicinity of the reader and also derives additional reader information corresponding to the RFID transponder. In normal mode, the reader compares the ID codes stored in memory to the RFID signal returned from an RFID transponder in the vicinity of said the reader. The RFID reader behavior is at least in part determined by the additional reader information corresponding to said ID codes stored in memory. We also describe a confidence threshold for acceptance of an ID code in learn mode and normal mode. The confidence threshold in normal mode may be less than in learn mode. | 12-30-2010 |
20110241750 | TUNED RESONANT CIRCUITS - A circuit block which comprises a non-linear capacitor with two different values of capacitance dependent on a value of a voltage of a resonant signal on the capacitor; a plurality of second capacitors each coupled to a respective switch to enable a said second capacitor to be switched in or out of parallel connection with the nonlinear capacitor; and a tuning control, coupled to the second capacitor switches, and sensing an amplitude of the resonant signal. The tuning control circuit is configured to control the second capacitor switches to successively switch the second capacitors in/out of parallel connection with the non-linear capacitor dependent on the amplitude of the resonant signal until the non-linear capacitor has substantially a single one of two different values, such that in a resonant circuit the circuit block then behaves as a fixed value capacitor. | 10-06-2011 |
20120272696 | RFID PET DOOR - Embodiments of the invention relate to the field of pet doors, particularly selective entry pet doors based on detection of RFID tags. An RFID pet door, the pet door comprising: an RFID reader to read an RFID tag on a pet; and a lock coupled to said RFID reader to control access through said pet door in response to an RFID signal from said tag; wherein said RFID reader has two modes, a first operational mode and a second, reduced power mode, and wherein said pet door further comprises: a pet proximity detector coupled to said RFID reader to identify when a pet is proximate said pet door and to control said RFID reader responsive to said identification such that when said pet is proximate said RFID is in said operational mode and such that said RFID reader is otherwise in said reduced power mode. | 11-01-2012 |
Patent application number | Description | Published |
20090198978 | Data processing apparatus and method for identifying sequences of instructions - A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction. | 08-06-2009 |
20110173433 | METHOD AND APPARATUS FOR TUNING A PROCESSOR TO IMPROVE ITS PERFORMANCE - A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved. | 07-14-2011 |
20110199118 | Power control of an integrated circuit including an array of interconnected configurable logic elements - An integrated circuit ( | 08-18-2011 |
20110268137 | COMMUNICATION WITHIN AN INTEGRATED CIRCUIT INCLUDING AN ARRAY OF INTERCONNECTED PROGRAMMABLE LOGIC ELEMENTS - An integrated circuit includes an array of interconnected programmable logic elements ( | 11-03-2011 |
20110271126 | Data processing system - A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units. | 11-03-2011 |
20140237281 | DATA PROCESSING SYSTEM - A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units. | 08-21-2014 |