Patent application number | Description | Published |
20090082235 | Oxidative Stable Oil Formulation - Oxidation stable oil formulation comprising a base oil composition comprising a mineral-derived naphthenic base oil, a mineral-derived paraffinic base oil, and/or a Fischer-Tropsch derived paraffinic base oil, a copper passivator and at most 0.1 wt % of an organic sulphur or phosphorus anti-wear additive. | 03-26-2009 |
20090137435 | Electrical Oil Formulation - Electrical oil formulation comprising a base oil component and an additive, wherein (i) at least 80 wt % of the base oil component is a paraffin base oil having a paraffin content of greater than 80 wt % paraffins and a saturates content of greater than 98 wt % and comprising a series of iso-paraffins having n, n+1, n+2, n+3 and n+4 carbon atoms and wherein n is between 20 and 35; and (ii) an anti-oxidant additive; wherein the base oil component has a flash point of at least 170° C., as determined by ISO 2592. | 05-28-2009 |
20100016190 | ELECTRICAL OIL COMPOSITION - An electrical oil composition comprising: A) dc-asphalted cylinder oil (DACO) having a benzo [a] pyrene content of not more than 1 mg/kg and a total content of benz [a] anthracene, chrysene, benzo [b] fluoranthene, benzo [j] fluoranthene, benzo [k] fluoranthene, benzo [c] pyrene, benzo [a] pyrene and dibenz [a, h] anthracene of not more than 10 mg/kg; and B) one or more base oils each having a viscosity of not more than 4.0 mm | 01-21-2010 |
Patent application number | Description | Published |
20140058042 | UNSATURATED POLYESTER RESIN COMPOSITION - The present invention relates to an unsaturated polyester resin composition comprising (a) an unsaturated polyester, (b) a vinyl group containing organic compound as reactive diluent and (c) a transition metal compound, wherein the resin composition comprises (d) a compound according to formula (1) as reactive diluent | 02-27-2014 |
20140066581 | PROCESS FOR RADICALLY CURING A COMPOSITION - The present invention relates to a process for radically curing a composition comprising a methacrylate containing compound (a1) and a monomer copolymerizable with said methacrylate containing compound in the presence of a 5 transition metal compound (c) and a peroxide, wherein the composition comprises a compound (b) according to formula (1) as monomer copolymerizable with said methacrylate containing compound whereby n=0-3; R | 03-06-2014 |
20140073742 | UNSATURATED POLYESTER RESIN COMPOSITION - The present invention relates to unsaturated polyester resin compositions comprising (a) an unsaturated polyester, (b) a vinyl group containing organic compound as reactive diluent and (c) a tertiary aromatic amine, wherein the resin composition further comprises (d) a compound according to formula (1) as reactive diluent | 03-13-2014 |
20140087111 | PROCESS FOR RADICALLY CURING A COMPOSITION - The present invention relates to a process for radically curing a composition comprising a methacrylate containing compound (a1) and a monomer copolymerizable with said methacrylate containing compound in the presence of tertiary aromatic amine (c) and a peranhydride (d), wherein the composition comprises a compound (b) according to formula (1) as monomer copolymerizable with said methacrylate containing compound | 03-27-2014 |
20140309378 | RESIN COMPOSITION - This invention relates to an unsaturated polyester resin composition characterized in that the resin composition comprises a. An unsaturated polyester resin comprising fumaric, maleic and/or itaconic building blocks, b. At least one vinyl ester as reactive diluent, c. An iron complex and/or salt, and d. A ligand according to the following formula (1) wherein each R | 10-16-2014 |
Patent application number | Description | Published |
20100125620 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM. | 05-20-2010 |
20100125621 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths. | 05-20-2010 |
20110055307 | METHOD FOR FLOATING POINT ROUND TO INTEGER OPERATION - An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask. | 03-03-2011 |
20130282784 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM. | 10-24-2013 |
Patent application number | Description | Published |
20120278591 | CROSSBAR SWITCH MODULE HAVING DATA MOVEMENT INSTRUCTION PROCESSOR MODULE AND METHODS FOR IMPLEMENTING THE SAME - A microprocessor is provided that has a datapath that is split into upper and lower portions. The microprocessor includes a centralized crossbar switch module having a single data movement module. The data movement module is capable of processing instructions that require operands to be exchanged between upper and lower 64-bit halves of the split architecture. The data movement module can access and process all instructions that require simultaneous access to the entire register contents of the upper and lower portions. The data movement module is configured to execute any one of a number of different instructions to perform data manipulation with respect to one or more “split-operands” (also referred to simply as “operands” herein). The data movement module can exchange data (bytes and/or bits) of operands for the upper and lower 64-bit halves so that bytes and/or bits of operands can be moved or rearranged to other positions during execution of a particular instruction. The data movement module can allow for various types of operand data movement/manipulation that may be required to implement instruction processing that may be required per various instructions, such as permute, pack, shuffle, vectored conditional move, extract, shift, rotate instructions, any other instruction in which operand data is manipulated, shifted, moved, re-ordered, shuffled or scrambled. | 11-01-2012 |
20130007075 | METHODS AND APPARATUS FOR COMPRESSING PARTIAL PRODUCTS DURING A FUSED MULTIPLY-AND-ACCUMULATE (FMAC) OPERATION ON OPERANDS HAVING A PACKED-SINGLE-PRECISION FORMAT - The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced. | 01-03-2013 |
20130060828 | FLOATING POINT MULTIPLY ACCUMULATOR MULTI-PRECISION MANTISSA ALIGNER - A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. | 03-07-2013 |
Patent application number | Description | Published |
20120265793 | MERGED COMPRESSOR FLOP CIRCUIT - A merged compressor flip-flop circuit is provided. The circuit includes a compressor circuit having a front-end and a back-end, the front-end configured to receive four input bits and to output a first carry-bit to a back-end of a second compressor circuit, the front end further configured to output intermediate sum signals to the back-end of the compressor circuit, the back-end configured to receive the intermediate sum signals from the front-end and further configured to receive a second carry-bit from a front-end of a third compressor circuit, the back-end further configured to output a sum-bit and a third carry-bit based upon the intermediate sum signals and the second carry-bit, and a flip-flop circuit configure to receive the sum-bit and third carry-bit and to store the sum-bit and third carry-bit, wherein the back-end of the compressor circuit directly drives the sum-bit and third carry-bit into the flip-flop circuit | 10-18-2012 |
20130346463 | METHOD AND APPARATUS FOR MULTIPLY INSTRUCTIONS IN DATA PROCESSORS - The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced. | 12-26-2013 |
20140136587 | FLOATING POINT MULTIPLY-ADD UNIT WITH DENORMAL NUMBER SUPPORT - The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum. | 05-15-2014 |