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Hilgendorf
Rolf Hilgendorf, Boeblingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20090044030 | APPARATUS FOR DYNAMIC POWER MANAGEMENT IN AN EXECUTION UNIT USING PIPELINE WAVE FLOW CONTROL - Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit. | 02-12-2009 |
Rolf Hilgendorf, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080226008 | Providing Accurate Time-Based Counters for Scaling Operating Frequencies of Microprocessors - The illustrative embodiments provide accurate time-based counters for scaling operating frequencies of microprocessors. A time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment. | 09-18-2008 |
Rolf Bernhard Hilgendorf, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100229176 | Distribute Accumulated Processor Utilization Charges Among Multiple Threads - A utilization analyzer acquires accumulator values from multiple accumulators. Each accumulator corresponds to a particular processor thread and also corresponds to a particular processor utilization resource register (PURR). The utilization analyzer identifies, from the multiple accumulators, a combination of equal accumulators that each includes a largest accumulator value. Next, the utilization analyzer selects a subset of processor utilization resource registers from a combination of processor utilization resource registers that correspond to the combination of equal accumulators. The subset of processor utilization resource registers omits at least one processor utilization resource register from the combination of utilization resource registers. In turn, the utilization analyzer increments each of the subset of utilization resource registers. | 09-09-2010 |