Higashi, Kawasaki
Akihiro Higashi, Kawasaki JP
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20150022686 | FLICKER DETECTION METHOD AND FLICKER DETECTION APPARATUS - The present invention discloses a flicker detection method and a flicker detection apparatus. The method includes: calculating the mean values of selected rows of image frames to constitute a mean value vector; calculating a differential vector between the mean value vectors of a current frame and a previous frame; calculating a DC-free difference vector by subtracting a direct current component from respective elements of the differential vector; calculating a power spectrum corresponding to the DC-free difference vector; obtaining a first frequency reference value; obtaining a second frequency reference value; and if the difference between the first and second frequency reference values is above a threshold, then it is determined that flicker is present in the current frame; otherwise, it is determined that no flicker is present. | 01-22-2015 |
Hidenori Higashi, Kawasaki JP
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20090006893 | Information processing apparatus, diagnosis method, and computer program product - A logical central processing unit (logical CPU) selects a target device. When the target device is shared by another logical CPU, the logical CPU determines whether the logical CPU is in charge of exclusively making diagnosis of the target device. When the target device is not shared by another logical central processing unit or when the logical CPU is exclusively in charge of making diagnosis of the target device, the logical CPU makes diagnosis of the target device and stores a result of diagnosis in a storage unit. | 01-01-2009 |
Hideto Higashi, Kawasaki JP
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20100085222 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PRODUCT - A computer-readable recording medium stores therein an information processing program that causes a computer to execute storing an aggregate of layers of nodes respectively having a pointer to an upper node, pointers to a leaf and/or a lower node and branches to lower nodes; obtaining a totaling result of appearance frequencies of character codes described in a file; classifying the character codes by layer, based on appearance probabilities thereof and the totaling result; calculating, based on a quantity of character codes in an ith layer and for the ith layer, a quantity of pointers pointing to leaves, and based on the quantity calculated and for the ith layer, further calculating a number of times nodes are used and a quantity of pointers pointing to lower nodes; generating, based on calculation results, a Huffman tree; and converting the Huffman tree into a node-less Huffman tree and storing the node-less Huffman tree. | 04-08-2010 |
Hirohito Higashi, Kawasaki JP
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20080252387 | OSCILLATOR - There is provided an oscillator having first and second oscillating units ( | 10-16-2008 |
20090167446 | VOLTAGE CONTROLLED RING OSCILLATOR - There is provided a voltage controlled ring oscillator having a plurality of ring-connected amplifiers ( | 07-02-2009 |
20090189655 | PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT - A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage. | 07-30-2009 |
Koichiro Higashi, Kawasaki JP
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20110228685 | WIRELESS NETWORK CONTROL DEVICE, WIRELESS NETWORK CONTROL METHOD, AND WIRELESS NETWORK CONTROL SYSTEM - A buffer has a predetermined storage capacity, and accumulates data received from an external device. A transmitting unit reads data from the buffer and transmits the data to a mobile terminal. A transmission rate determining unit determines the transmission rate for transmitting data from the external device to its own device, based on the free space in the buffer. The window size notifying unit notifies the mobile terminal of a window size in accordance with the determined transmission rate. | 09-22-2011 |
Kouichirou Higashi, Kawasaki JP
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20110211471 | PACKET TRANSMISSION METHOD AND NODES - This is a method for transmitting packets. The transmission method includes measuring a time taken for feedback indicating that a packet including context information has been lost; and switching between a first mode and a second mode based on the measured time taken for the feedback, the first mode being a mode for periodically transmitting a packet including the context information and the second mode being a mode for transmitting a packet including the context information in response to the feedback indicating that a packet including the context information has been lost. | 09-01-2011 |
Osamu Higashi, Kawasaki JP
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20100223775 | METHOD FOR DISMOUNTING ELECTRONIC DEVICE - A method for dismounting an electronic device that is mounted on a printed board by solder including heating the electronic device by dipping the electronic device in inert liquid heated in a heating bath and melting the solder in the through-hole using heat transferred from the electronic device. The electronic device has a terminal pin disposed in a through-hole of the printed board extending from a front surface to a back surface of the printed board. The terminal pin is joined to the printed board by the solder. | 09-09-2010 |
20100254426 | HEAT SINK FOR MEASURING TEMPERATURE OF ELECTRONIC COMPONENT - There is provided a heat sink for measuring temperature of electronic component. The heat sink includes a heat radiating plate, a fin, a heat receiving plate, and a temperature detector. The heat radiating plate has a first surface that receives heat from the electronic component. The fin is for radiating heat energy conducting through the heat radiating plate and is connected to the heat radiating plate. The heat receiving plate arranged apart from the heat radiating plate has a second surface movable to be parallel to the first surface. The temperature detector that detects a temperature is disposed on the heat receiving plate. | 10-07-2010 |
20110072655 | METHOD OF SOLDERING AN ELECTRONIC COMPONENT - A soldering method of an electronic component includes inserting pins of the electronic component into through-holes provided in a printed circuit board; preheating interiors of the through-holes with an inert fluid; and bonding the pins to the through-holes by exposing molten solder to the preheated through-holes. | 03-31-2011 |
Yusuke Higashi, Kawasaki JP
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20160079434 | SEMICONDUCTOR DEVICE - This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film. | 03-17-2016 |
20160085627 | Memory System, Error Correction Device, and Error Correction Method - According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data. | 03-24-2016 |
20160088243 | IMAGING ELEMENT, IMAGING APPARATUS, AND SEMICONDUCTOR APPARATUS - According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel. | 03-24-2016 |