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Hieu
Hieu Lam, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090152235 | METHOD OF MANUFACTURING A PERPENDICULAR MAGNETIC WRITE HEAD WITH STEPPED TRAILING MAGNETIC SHIELD WITH ELECTRICAL LAPPING GUIDE CONTROL - A method for manufacturing a magnetic write head having a stepped trailing shield. The stepped trailing shield is formed by forming a non-magnetic bump over a write pole prior to electroplating a wrap-around magnetic shield. The method allows the location of the front edge of the bump relative to the back edge of the wrap-around shield to be monitored by measuring the electrical resistance of an electrical lapping guide formed concurrently with these features. This concurrent formation of a lapping guide can be used to define the relative location of other features as well, such as the location of a back edge of a wrap-around shield relative to a flare point of a write pole. | 06-18-2009 |
| 20090168260 | Layered return poles for magnetic write heads - Methods and structures for the fabrication of both thin film longitudinal and perpendicular write heads are disclosed. A unique feature of these write heads is the inclusion of layered return poles, which comprise alternating layers of 22/78 and 80/20 NiFe alloys. The alternating layers also vary in thickness, the 22/78 NiFe layers having a nominal thickness of 1500 angstroms and the 80/20 NiFe layers having a nominal thickness of about 75 angstroms. Head efficiency and signal to noise ratios are significantly improved in heads having layered return pole construction. | 07-02-2009 |
| 20100107402 | Methods Of Making Magnetic Write Heads With Use Of A Resist Channel Shrinking Solution Having Corrosion Inhibitors - One preferred method for use in making a device structure with use of the resist channel shrinking solution includes the steps of forming a first pedestal portion within a channel of a patterned resist; applying a resist channel shrinking solution comprising a resist channel shrinking film and corrosion inhibitors within the channel of the patterned resist; baking the resist channel shrinking solution over the patterned resist to thereby reduce a width of the channel of the patterned resist; removing the resist channel shrinking solution; and forming a second pedestal portion within the reduced-width channel of the patterned resist. Advantageously, the oxide layer and the corrosion inhibitors of the resist channel shrinking solution reduce corrosion in the pedestal during the act of baking the resist channel shrinking solution. | 05-06-2010 |
Hieu Nguyen, Palmdale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090139206 | Dual-mode chemical-electric thrusters for spacecraft - Spacecraft thrusters capable of dual-mode operation, and a method of applying s propulsion to a spacecraft using a dual-mode thruster are provided. In one embodiment, the thrusters of the current invention can operate as a chemical motor to provide high thrust and low propellant exhaust velocity to achieve fast maneuverability, or as an electric propulsion thruster to provide low thrust and high exhaust velocity to perform maneuvers with a minimal amount of propellant. | 06-04-2009 |
Hieu Trong Huynh, Pflugerville, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090106607 | Method and Apparatus for SRAM Macro Sparing in Computer Chips - SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros. | 04-23-2009 |