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Hierlemann
Andreas Hierlemann, Zurich CH
| Patent application number | Description | Published |
|---|---|---|
| 20090261845 | ENANTIOSELECTIVE CAPACITIVE SENSOR - The present invention relates to an enantioselective capacitive sensor, its manufacture and use and to devices comprising such sensors. | 10-22-2009 |
| 20100276734 | ELECTROCHEMICAL BIOSENSOR ARRAYS AND SYSTEMS AND METHODS OF MAKING SAME - Electrochemical biosensor arrays and systems, as well as methods of making the electrochemical biosensor arrays and systems, are described herein. The electrochemical biosensor systems can be used with CMOS detection circuits that have a plurality of chemical detection and/or actuation channels or sites. The biosensor systems generally include a first inert conducting electrode disposed on a first portion of a CMOS detection circuit and a polymeric layer adjacent the first inert conducting electrode. The biosensor systems can also include a capture biomolecule bound to the polymeric layer. The biosensor system can also include the CMOS detection and/or actuation circuit having a plurality of channels. | 11-04-2010 |
Helmut Hierlemann, Göppingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20090220577 | Moulded body for medically treating wounds - The invention relates to an absorbable and porous shaped article for the medical treatment of wounds, in particular large, deep wounds with heavy discharge, where the shaped article is in the form of a foam structure which includes a co- and/or terpolymer based on the monomers lactide, triethylene carbonate, ε-caprolactone and/or dioxan-2-one. | 09-03-2009 |
Helmut Hierlemann, Göppingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20090220577 | Moulded body for medically treating wounds - The invention relates to an absorbable and porous shaped article for the medical treatment of wounds, in particular large, deep wounds with heavy discharge, where the shaped article is in the form of a foam structure which includes a co- and/or terpolymer based on the monomers lactide, triethylene carbonate, ε-caprolactone and/or dioxan-2-one. | 09-03-2009 |
Matthias Hierlemann, Karlsfeld DE
| Patent application number | Description | Published |
|---|---|---|
| 20100314619 | Test Structures and Methods for Semiconductor Devices - Test structures for semiconductor devices, methods of forming test structures, semiconductor devices, methods of manufacturing thereof, and testing methods for semiconductor devices are disclosed. In one embodiment, a test structure for a semiconductor device includes at least one first contact pad disposed in a first material layer in a scribe line region of the semiconductor device. The at least one first contact pad has a first width. The test structure also includes at least one second contact pad disposed in a second material layer proximate the at least one first contact pad in the first material layer. The at least one second contact pad has a second width that is greater than the first width. | 12-16-2010 |
| 20110095413 | Method and Apparatus for Semiconductor Device Fabrication Using a Reconstituted Wafer - Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame. | 04-28-2011 |
Matthias Hierlemann, Fishkill, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080283927 | Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit - System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment comprises manufacturing an integrated circuit, comprising forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al | 11-20-2008 |
| 20110037146 | Capacitors and Methods of Manufacture Thereof - Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device. | 02-17-2011 |
| 20110089501 | Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit - A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed. | 04-21-2011 |
Matthias Hierlemann, Munich DE
| Patent application number | Description | Published |
|---|---|---|
| 20080213993 | Method and Apparatus of Stress Relief in Semiconductor Structures - A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer. | 09-04-2008 |