Patent application number | Description | Published |
20090097329 | Semiconductor storage device and high-speed address-latching method - A semiconductor storage device includes: an input buffer that receives address data and command data; a first through-latch-type latch circuit that latches the command data in synchronism with a rising edge of a clock signal; and a second through-latch-type latch circuit that latches the address data in synchronism with a falling edge of the clock signal. | 04-16-2009 |
20090097330 | Fuse latch circuit and fuse latch method - A fuse latch circuit starts a precharge operation for reading out a state of a fuse element when receiving an external command which is a command to reset an operation mode register (MRS reset command) after power-on, and reads out and latches the state of the fuse element after completion of the precharge operation. | 04-16-2009 |
20090108897 | SEMICONDUCTOR DEVICE AND TIMING CONTROL METHOD FOR THE SAME - A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit. | 04-30-2009 |
20100045359 | CALIBRATION CIRCUIT - To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT | 02-25-2010 |
20100177588 | CALIBRATION CIRCUIT AND CALIBRATION METHOD - A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers in synchronization with the internal clock. According to the present invention, because a calibration operation that does not depend on an external clock is performed, even when a frequency of the external clock is changed according to an operation mode or the like, it is possible to maintain a constant period of time given to a single adjustment step or a constant time required for a series of calibration operations. | 07-15-2010 |
20110084404 | Semiconductor device - One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit. | 04-14-2011 |
20110084729 | Semiconductor device - One interface chip and a plurality of core chips are electrically connected via a plurality of through silicon vias. A data signal of a driver circuit is input into the core chip via any one of the through silicon vias. An output switching circuit activates any one of tri-state inverters and selects one of the through silicon vias. The tri-state inverters amplify the data signal and transmit it to the through silicon via. Similarly, an input switching circuit activates any one of tri-state inverters. These tri-state inverters also amplify the data signal transmitted from the through silicon via and supply it to the receiver circuit. | 04-14-2011 |
20110085404 | Semiconductor memory device and information processing system including the same - The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used. | 04-14-2011 |
20110093224 | Semiconductor device, semiconductor device testing method, and data processing system - To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal. | 04-21-2011 |
20110093735 | Semiconductor memory device, method of adjusting the same and information processing system including the same - Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side. | 04-21-2011 |
20110141828 | SEMICONDUCTOR SYSTEM - To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced. | 06-16-2011 |
20110175639 | Semiconductor device semiconductor device testing method, and data processing system - To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. | 07-21-2011 |
20120195136 | Semiconductor device - A semiconductor device according to the present invention includes plural controlled chips CC | 08-02-2012 |
20120195148 | Semiconductor device and information processing system including the same - A semiconductor device according to the present invention includes plural core chips CC | 08-02-2012 |
20120305917 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters. | 12-06-2012 |
20120320653 | SEMICONDUCTOR SYSTEM - A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 12-20-2012 |
20120320654 | SEMICONDUCTOR SYSTEM - A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 12-20-2012 |
20140056086 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF ADJUSTING THE SAME AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells. | 02-27-2014 |
20140169057 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM HAVING THE SAME - A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address. | 06-19-2014 |
20140344612 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE TESTING METHOD, AND DATA PROCESSING SYSTEM - To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. | 11-20-2014 |