Patent application number | Description | Published |
20110254073 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer. | 10-20-2011 |
20120020165 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - In one embodiment, there is provided a semiconductor storage device including: a memory cell array; a high voltage generator; and a controller that controls the high voltage generator. When a word line to is selected from word lines, the controller controls the high voltage generator to: apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line; apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage; and apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word line and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage. | 01-26-2012 |
20120175695 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a memory cell comprising a charge accumulate layer above a semiconductor substrate and a control gate above the charge accumulate layer. The charge accumulate layer is capable of accumulating charges therein. The control gate is configured to control an amount of the charges accumulated in the charge accumulate layer. The control gate comprises a lower-layer control gate part of metal or metallic silicide which is processable by etching, and an upper-layer control gate part of a material different from that of the lower-layer control gate part. | 07-12-2012 |
20120175725 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a memory cell array provided on a semiconductor substrate and comprising a plurality of memory cells configured to store data therein, and a peripheral circuit part provided on the semiconductor substrate and configured to control the memory cell array. An element isolation part is provided between active areas where the memory cells and the peripheral circuit part are formed. A sidewall film is provided on a side surface of the active area in the peripheral circuit part. | 07-12-2012 |
20120211860 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation. | 08-23-2012 |
20120217571 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction. | 08-30-2012 |
20130228842 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer. | 09-05-2013 |
20150063025 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory cell string stacked body includes first memory cell transistors above a semiconductor substrate, and second memory cell transistors below a first channel semiconductor film, and one of the first memory cell transistors and one of the second memory cell transistors share with a control gate electrode. The control gate electrodes of the first memory cell transistors cover an upper surface of a first charge storage layer and at least a part of a side surface in a second direction via a first insulating film in the one of the first memory cell transistors. The control gate electrodes of the second memory cell transistors cover only a lower surface of a second charge storage layer via a second insulating film in one of the second memory cell transistors. | 03-05-2015 |