Patent application number | Description | Published |
20090006725 | MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer. | 01-01-2009 |
20090010057 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM - A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2 | 01-08-2009 |
20090290415 | CARD CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits. | 11-26-2009 |
20090292863 | MEMORY SYSTEM WITH A SEMICONDUCTOR MEMORY DEVICE - A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device. | 11-26-2009 |
20100042777 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD FOR THE SAME - A semiconductor device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first memory block configured to hold at least 2 bits data, and a second memory block configured to hold 1-bit data. The data is programmed into the first and second memory blocks in units of page. Each of the pages in the first memory block is assigned to a corresponding bit of the held data. Time required for write varies depending on the bit. The controller instructs the nonvolatile semiconductor memory to program the write data into the first memory block or the second memory block. The controller instructs the nonvolatile semiconductor memory to program the data on any of the pages in the second memory block if a final page of the write data corresponds to the bit requiring the longest time for the write. | 02-18-2010 |
20100271876 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM - A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2 | 10-28-2010 |
20110185225 | MEMORY SYSTEM WITH NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued. | 07-28-2011 |
20110280071 | CARD CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits. | 11-17-2011 |
20120137057 | MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer. | 05-31-2012 |
20120281473 | CARD CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits. | 11-08-2012 |
20140006906 | MEMORY DEVICE | 01-02-2014 |
20140047162 | MEMORY SYSTEM CAPABLE OF PREVENTING DATA DESTRUCTION - According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level02-13-2014 | |
20150063034 | MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY - According to one embodiment, a memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a storage area having a plurality of memory cells configured to store data. The control circuit determines whether data write to the storage area is possible or impossible. | 03-05-2015 |