# Hideo Shimizu, Kanagawa JP

## Hideo Shimizu, Kanagawa JP

Patent application number | Description | Published |
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20080215955 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory configured to store data at a first address and store an error detecting code corresponding to the data at a second address which is set up in a predetermined relation with the first address and different from the first address; and an address storage portion configured to store information on address relation between the first address and the second address. | 09-04-2008 |

20090024887 | SEMICONDUCTOR STORAGE DEVICE, DATA WRITE METHOD AND DATA READ METHOD - A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written, and a storage unit configured to store the data and the error detecting code in the memory cell. | 01-22-2009 |

20100137615 | Homogeneous Asymmetric Hydrogenation Process - Provide that a useful catalyst for homogeneous hydrogenation, particularly a catalyst for homogeneous asymmetric hydrogenation for hydrogenation, particularly asymmetric hydrogenation, which is obtainable with comparative ease and is excellent in economically and workability, and a process for producing a hydrogenated compound of an unsaturated compound, particularly an optically active compound using said catalyst with a high yield and optical purity. | 06-03-2010 |

20100168440 | Homogeneous Asymmetric Hydrogenation Process - Provide that a useful catalyst for homogeneous hydrogenation, particularly a catalyst for homogeneous asymmetric hydrogenation for hydrogenation, particularly asymmetric hydrogenation, which is obtainable with comparative ease and is excellent in economically and workability, and a process for producing a hydrogenated compound of an unsaturated compound, particularly an optically active compound using said catalyst with a high yield and optical purity. | 07-01-2010 |

20120069997 | ENCRIPTION DEVICE AND DECRYPTION DEVICE - According to one embodiment, an encryption device includes a storage unit, an input unit, first to fourth partial encryption units, a generation unit, and an output unit. The first partial encryption unit calculates first intermediate data from input plain data to store in the storage unit. The generation unit generates a round key, which is used in calculations for the first intermediate data and N-th intermediate data, from the secret key. The second partial encryption unit calculates (i+1)th intermediate data from i-th intermediate data (i is smaller than N) and the round key to store in the storage unit. The third partial encryption unit performs an arithmetic operation including predetermined conversion for mixing the N-th intermediate data, and calculates (N+1)th intermediate data to store in the storage unit. The fourth partial encryption unit obtains encrypted data by performing an arithmetic operation including inverse conversion of the conversion on the (N+1)th intermediate data. | 03-22-2012 |

20120069998 | ENCRYPTION DEVICE - According to one embodiment, in an encryption device, a segmentation unit segments masked plain data into pieces of first segmented data. A first processing unit generates pieces of second segmented data from the pieces of first segmented data. A nonlinear transform unit generates pieces of third segmented data transformed from the pieces of second segmented data. A data integration unit integrates fourth segmented data to generate masked encrypted data. An unmask processing unit generates encrypted data from the masked encrypted data. The exclusive OR of the pieces of second segmented data matches the exclusive OR of input data, subjected to nonlinear transform processing and calculated from the plain data, and the first mask. The exclusive OR of the pieces of third segmented data matches the exclusive OR of transform data, obtained when the nonlinear transform processing is performed on the input data, and the second mask. | 03-22-2012 |

20120131078 | ARITHMETIC DEVICE - According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p. | 05-24-2012 |

20120307997 | ENCRYPTION DEVICE - According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1. | 12-06-2012 |

20130202105 | ARITHMETIC DEVICE - According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and based on an offset which is a value corresponding to a counter value and which is based on the address of the first piece of data, the address generating unit generates addresses of the memory device. The control unit controls the arithmetic processing unit in such a way that the arithmetic processing is done in a sequence determined in the encryption method, and that specifies an update of the counter value at a timing of modifying the type of data and at a timing of modifying data. | 08-08-2013 |