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Hideo Aoki

Hideo Aoki, Yokohama-Shi JP

Patent application numberDescriptionPublished
20090007426Image forming apparatus and method of manufacturing electronic circuit using the same - An image forming apparatus comprises an exposure unit forming an electrostatic latent image on a photo conductor based on image information, a developing unit developing the electrostatic latent image by toner made of formation material of a circuitry layer, and an electrostatic transferring unit transferring a toner image on the photo conductor onto a substrate. The toner image is transferred so as to cover at least a part of a conductor layer formed on the substrate. At this time, excessive charges caused in the conductor layer accompanying the start of the transfer of the toner image are removed. Alternatively, charges of which polarity is reverse to that of the toner are added to the conductor layer. These allow the circuitry layer to be formed to have a desired pattern favorably and securely on the conductor layer.01-08-2009
20090256884IMAGE FORMING APPARATUS - An image forming apparatus includes a recording head to eject ink droplets through a nozzle onto a recording medium, a replaceable ink cartridge to contain ink to be supplied to the recording head, a replaceable waste-ink tank to store waste ink ejected from the recording head, a cartridge mounting portion provided on a front side of the image forming apparatus and configured to accommodate the ink cartridge, including a first opening through which the ink cartridge is inserted, a tank mounting portion provided on the front side of the image forming apparatus, adjacent to the cartridge mounting portion, and configured to accommodate the waste-ink tank and to include a second opening through which the waste-ink tank is inserted, and an openably closable cartridge cover disposed on the front side of the image forming apparatus, configured to cover both the first opening and the second opening.10-15-2009
20100000083METAL-CONTAINING RESIN PARTICLE, RESIN PARTICLE, ELECTRONIC CIRCUIT SUBSTRATE, AND METHOD OF PRODUCING ELECTRONIC CIRCUIT - According to one mode of the present invention, metal-containing resin particles comprising a resin containing a thermosetting resin at 50 wt % or more and having a rate of moisture absorption from 500 to 14500 ppm, and fine metal particles contained in the resin, is provided.01-07-2010
20100320258METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.12-23-2010
20110076801METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.03-31-2011

Patent applications by Hideo Aoki, Yokohama-Shi JP

Hideo Aoki, Sagamihara-Shi JP

Patent application numberDescriptionPublished
20100234530POWDERY PROCESSING AID FOR POLYOLEFIN RESINS, METHOD FOR PRODUCING THE SAME, RESIN COMPOSITION AND SHAPED ARTICLE TECHNICAL FIELD - Disclosed are a powdery processing aid for polyolefin resins, containing an alkyl methacrylate polymer which has alkyl methacrylate units having an alkyl group with 2 to 6 carbon atoms as a main component and has a mass average molecular weight of 150,000 to 20,000,000, having good handling properties as a powder, having good dispersibility in polyolefin resins, and being able to improve shaping processability of polyolefin resins; and a polyolefin resin composition having improved shaping processability, which contains a powdery processing aid for polyolefin resins and a polyolefin resin.09-16-2010

Hideo Aoki, Tokyo JP

Patent application numberDescriptionPublished
20080303158SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.12-11-2008
20100203724METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.08-12-2010

Patent applications by Hideo Aoki, Tokyo JP

Hideo Aoki, Kanagawa JP

Patent application numberDescriptionPublished
20090074494COMPACT FRONT-OPERABLE IMAGE FORMING APPARATUS - An image forming apparatus is disclosed that includes a substantially flat top face and a slanted front face, the bottom side of which recedes backward. The image forming apparatus may includes a paper discharge tray disposed at a lower portion of the slanted front face, the paper discharge tray protruding forward. The paper discharge tray may be tiltable upward and downward. Because the bottom side of the slanted front face recedes backward, the flat top face can be provided, and simultaneously, enough space for the feeding and discharging of paper can be secured.03-19-2009

Hideo Aoki, Yokohama JP

Patent application numberDescriptionPublished
20080209069Congestion control and avoidance method in a data processing system - A congestion control and avoidance method including a method check step of determining whether the request contents is cacheable or uncacheable on the basis of the request inputted from the client terminal, a first Uniform Resource Identifier (URI) check step of, when it is determined that the request contents is cacheable in the method check step, checking a URI included in the request from the client terminal to determine whether the request contents is cacheable or uncacheable, a first URI hash search step of, when it is determined that the request contents is cacheable based on determination of the first URI check step, searching a URI hash to determine to execute any of regular caching, priority caching and access limitationing operation, and a step of executing any of the regular caching, priority caching and access limitationing operation according to determination in the first URI hash search step.08-28-2008