| Patent application number | Description | Published |
|---|
| 20090030961 | Microprocessor performing IIR filter operation with registers - A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R | 01-29-2009 |
| 20090037702 | Processor and data load method using the same - A processor includes an instruction decoder, an instruction execution part and a register file. The instruction decoder is adapted to decode an instruction. The instruction execution part is adapted to execute processing corresponding to the instruction decoded by the instruction decoder. The register file is capable of storing load data from a data memory and supplying input data to the instruction execution part. The register file includes a plurality of registers, each of which is capable of holding a plurality of bits of data. Furthermore, the register file is configured to update the data held by the plurality of registers by shifting the data held by the plurality of registers among the plurality of registers. | 02-05-2009 |
| 20090063808 | Microprocessor and method of processing data - A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part. | 03-05-2009 |
| 20090070569 | BRANCH PREDICTION DEVICE,BRANCH PREDICTION METHOD, AND MICROPROCESSOR - A branch prediction device predicts a branching probability in which a branch condition of a conditional branch instruction read out from an instruction memory storing an instruction is satisfied. A branch prediction entry part included in the branch prediction device stores prediction information as to whether or not the branch condition of the conditional branch instruction is satisfied. An entry update part included in the branch prediction device predicts the branching probability when the conditional branch instruction is executed next time based on a branch direction and updates the prediction information when the branch condition is satisfied by executing the conditional branch instruction. | 03-12-2009 |
| 20090077154 | Microprocessor - Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2 | 03-19-2009 |
| 20100218022 | Processor system and operation mode switching method for processor system - A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group. | 08-26-2010 |
| 20100262402 | PERFORMANCE EVALUATION DEVICE AND PERFORMANCE EVALUATION METHOD - A performance evaluation device includes an event counter unit that counts events occurring by execution of an evaluation target program from arrival of a measurement start signal indicating a measurement start point of a measurement section preset to the evaluation target program to arrival of a measurement stop signal indicating a measurement stop point of the measurement section, and an iteration counter unit that counts iterations of the measurement section to be iterated based on at least one of the measurement start signal and the measurement stop signal. | 10-14-2010 |
