Patent application number | Description | Published |
20110049602 | NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A gate insulating film layer, a floating gate electrode layer, an interelectrode insulating film layer, and a control gate electrode layer are stacked on a silicon substrate, and the control gate electrode film layer is etched to form a plurality of the control gate electrodes having the same width with the width of the memory cell. An arbitrary of the plurality of control gate electrodes is a transistor unit, and an interelectrode insulating film, a floating gate electrode, and a gate insulating film are formed in the transistor unit. In the transistor unit, a conductive material is buried into a contact hole to form a transistor, the contact hole is formed along the plurality of control gate electrodes. | 03-03-2011 |
20110239096 | DATA MEMORY DEVICE AND METHOD OF PROGRAMMING TO THE SAME - A memory element array includes plural memory elements capable of storing M-value data (M is a natural number not smaller than 2). Among first to M-th data, the first data gives a largest physical impact on memory elements. | 09-29-2011 |
20120020160 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF - A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution. While the control circuit executes a voltage applying operation in memory cells to be maintained in an erased state, thereby moving a first threshold voltage distribution to a positive direction to obtain a third threshold voltage distribution representing the erased state. | 01-26-2012 |
20120106246 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF WRITING THE SAME, AND SEMICONDUCTOR DEVICE - A control circuit is configured to be able to perform a rough write process, a foggy write process, and a fine write process. The rough write process moves, for a memory cell to be provided with a plurality of second threshold voltage distributions, a first threshold voltage distribution in the positive direction to generate a third threshold voltage distribution. The foggy write process does not move, for a memory cell finally to be provided with first data, the third threshold voltage distribution, and moves, for a memory cell finally to be provided with second data different from the first data, the first threshold voltage distribution or the third threshold voltage distribution in the positive direction to generate a plurality of fourth threshold voltage distributions. The fine write process moves the fourth threshold voltage distributions in the positive direction to generate the second threshold voltage distributions. | 05-03-2012 |
20120236636 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to an embodiment includes a memory cell array and a control circuit configured to execute a read operation. The control circuit refers to data of a reference memory cell which is adjacent to a selected memory cell and in which data is written after a data write operation on the selected memory cell. The control circuit applies a first read pass voltage to a non-selected word line adjacent to the selected word line, when the data of the reference memory cell is data causing the shift of the threshold voltage of the selected memory cell. The control circuit applies a second read pass voltage lower than the first read pass voltage to the non-selected word line, when the data of the reference memory cell is data not causing the shift of the threshold voltage of the selected memory cell. | 09-20-2012 |
20120236637 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells are connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a write voltage to the word line. The control circuit is configured to execute a correction write operation accompanied by the write operation and executed on a selected memory cell, when a threshold voltage of data written in a reference memory cell is an erase level, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell. | 09-20-2012 |
20120243324 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a certain write voltage to the word line multiple times to set a threshold voltage of the memory cell to a value corresponding to data. The control circuit is configured to control the write voltage such that the write voltage is increased by a first step-up voltage when the write voltage is repeatedly applied in a first period after the write operation starts, and the write voltage is increased by a second step-up voltage lower than the first step-up voltage in a second period after the first period. | 09-27-2012 |
20130070532 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a control unit configured to perform a control of repeating a program operation, and a step-up operation, the program operation being an operation of applying a program pulse voltage to a selected memory cell and applying an intermediate voltage less than the program pulse voltage to first and second non-selected memory cells adjacent to the selected memory cell, and the step-up operation being an operation of increasing the program pulse voltage by a first step-up value. For a first period, the control unit maintains the intermediate voltage to be a constant value. For a second period, the control unit controls the step-up operation such that the intermediate voltage is increased by a second step-up value, and determines the first step-up value on the basis of the second step-up value. | 03-21-2013 |
20130077404 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages. | 03-28-2013 |
20130088924 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN - A bit line is electrically connected to one end of a current path of a memory cell. A word line is commonly connected to the memory cells arranged in a direction intersecting the bit line. A control circuit executes a write operation for applying a write voltage to the word line so shift a threshold voltage of the memory cell to be data written that the threshold voltage of the memory cell to be data written reaches a certain threshold voltage. During the write operation, the control circuit, while applying a gradually rising write voltage to the word line, gradually changes a voltage applied to the bit line based on a relationship between the threshold voltage of the memory cell to be written and a number of times of the write voltage applications. | 04-11-2013 |