| Patent application number | Description | Published |
|---|
| 20080244161 | Memory management apparatus and method for same - A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided for each of the plural ports. In this manner, monopolized use of the data memory by a specific port is prevented and each of the plural ports is securely provided with the use area of the data memory under control of the memory management apparatus. | 10-02-2008 |
| 20080303497 | Semiconductor integrated circuit device for providing series regulator - A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state. | 12-11-2008 |
| 20090009211 | Microcomputer and functional evaluation chip - A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit. | 01-08-2009 |
| 20090096504 | Data reception apparatus and microcomputer having the same - A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value. | 04-16-2009 |
| 20090106572 | Microcomputer system - A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer. | 04-23-2009 |
| 20090204841 | Periodic signal processing apparatus - A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task. | 08-13-2009 |
| 20100017585 | Microcomputer and encoding system for instruction code and CPU - A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed. | 01-21-2010 |
| 20100017641 | Communication system communication device and method for determining duty ratio of PWM control - A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication. | 01-21-2010 |
