Patent application number | Description | Published |
20090059674 | STORAGE APPARATUS, CONTROLLER AND CONTROL METHOD - Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device with more data write cycles than the flash memory, and a cache memory with faster access speed than the flash memory. Data provided from a host system is stored in the cache memory, this data is read from the cache memory at a prescribed timing, data read from the cache memory is stored in the disk-shaped memory device, and, when a prescribed condition is satisfied, this data is read from the disk-shaped memory device, and the data read from the disk-shaped memory device is stored in the flash memory. | 03-05-2009 |
20090077302 | Storage apparatus and control method thereof - This storage apparatus has a disk-shaped storage device for storing data sent from a host system, and includes a nonvolatile memory device for storing the data, a controller for controlling the reading or writing of the data sent from the host system from or into the disk-shaped storage device, and a device controller for controlling the nonvolatile memory device and the disk-shaped storage device. The device controller replicates data stored in the disk-shaped storage device to the nonvolatile memory device according to the usage of the disk-shaped storage device. The controller reads data from the nonvolatile memory device when the controller receives a data read request from the host system and corresponding data is stored in the nonvolatile memory device. | 03-19-2009 |
20090168784 | STORAGE SUBSYSTEM - Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule. | 07-02-2009 |
20090216965 | Storage device and access instruction sending method - A storage device for storing data sent from a host apparatus comprises a plurality of processors sending to a cache memory controller an access instruction relating to transmission of the data, based on an access request relating to the transmission of the data, the access request being sent from the host apparatus; and an access instruction sending unit exclusively sending to the cache memory the access instruction sent from the plurality of processors, wherein the access instruction sending unit includes a plurality of storage units for storing an access instruction which requires a response, and wherein when the access instruction which requires a response is stored in all of the storage units, the access instruction sending unit sends only an access instruction which requires a response to the cache memory controller. | 08-27-2009 |
20090249173 | Storage system and data storage method - The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device. | 10-01-2009 |
20110013625 | STORAGE SUBSYSTEM - Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule. | 01-20-2011 |
20110246720 | STORAGE SYSTEM WITH MULTIPLE CONTROLLERS - A first controller, and a second controller coupled to the first controller via a first path are provided. The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process. | 10-06-2011 |
20110296117 | STORAGE SUBSYSTEM AND ITS CONTROL METHOD - Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space. | 12-01-2011 |
20110296129 | DATA TRANSFER DEVICE AND METHOD OF CONTROLLING THE SAME - A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory. When a data transfer with a designated transfer length is completed, in order to confirm that writing is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the transfer by the procedure different from writing into the memory. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion. | 12-01-2011 |
20120023287 | STORAGE APPARATUS AND CONTROL METHOD THEREOF - This storage apparatus has a disk-shaped storage device for storing data sent from a host system, and includes a nonvolatile memory device for storing the data, a controller for controlling the reading or writing of the data sent from the host system from or into the disk-shaped storage device, and a device controller for controlling the nonvolatile memory device and the disk-shaped storage device. The device controller replicates data stored in the disk-shaped storage device to the nonvolatile memory device according to the usage of the disk-shaped storage device. The controller reads data from the nonvolatile memory device when the controller receives a data read request from the host system and corresponding data is stored in the nonvolatile memory device. | 01-26-2012 |
20130232284 | STORAGE SYSTEM AND DATA TRANSFER CONTROL METHOD - It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer. | 09-05-2013 |
20140104967 | INTER-MEMORY DATA TRANSFER CONTROL UNIT - A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprises an inter-memory data transfer control unit including an operation start trigger receiving unit, a parameter acquiring unit, a read unit, and a write unit. When the write unit detects switching of a write destination memory, the write unit confirms write completion as to the memory by a procedure different from writing. When a data transfer instructed by the processor is completed, the write unit confirms write completion as to the write destination memory at the end of the data transfer by the procedure different from writing. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion. | 04-17-2014 |
Patent application number | Description | Published |
20090098741 | METHOD FOR FORMING ULTRA-THIN BORON-CONTAINING NITRIDE FILMS AND RELATED APPARATUS - Boron-containing nitride films, including silicon boron nitride and boron nitride films, are deposited during, e.g., integrated circuit fabrication. The films are deposited in a process chamber having a reaction space that is defined as an open volume of the chamber directly above the substrate. The boron-containing nitride films are formed by flowing silicon and boron precursors into the process chamber while maintaining the volume, as measured under standard conditions, of silicon and boron precursors, e.g., SiH | 04-16-2009 |
20090155488 | SHOWER PLATE ELECTRODE FOR PLASMA CVD REACTOR - Methods and apparatuses for plasma chemical vapor deposition (CVD). In particular, a plasma CVD apparatus having a cleaning function, has an improved shower plate with holes having a uniform cross-sectional area to yield a high cleaning rate. The shower plate may serve as an electrode, and may have an electrically conductive extension connected to a power source. The shower plate, through which both cleaning gases and reaction source gases flow, may include a hole machined surface area with a size different than conventionally used to ensure a good film thickness uniformity during a deposition process. The size of the hole machined surface area may vary based on the size of a substrate to be processed, or the size of the entire surface of the shower plate. | 06-18-2009 |
20090162170 | TANDEM TYPE SEMICONDUCTOR-PROCESSING APPARATUS - A tandem type semiconductor-processing apparatus includes: a processing section including multiple units arranged in tandem, each of which unit includes a reaction chamber and a load lock chamber with an load lock interface; a FOUP section including at least one FOUP having a wafer cassette and a front opening interface; and a mini-environment section having a single interior connected to the processing section via each load lock interface on one side of the mini-environment section and connected to the FOUP section via each front opening interface on another side of the mini-environment section opposite to the one side. | 06-25-2009 |
20120028469 | METHOD OF TAILORING CONFORMALITY OF Si-CONTAINING FILM - A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness. | 02-02-2012 |
20120164846 | Method of Forming Metal Oxide Hardmask - A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula Si | 06-28-2012 |
20130014896 | Wafer-Supporting Device and Method for Producing SameAANM Shoji; FumitakaAACI Kawasaki-shiAACO JPAAGP Shoji; Fumitaka Kawasaki-shi JPAANM Fukuda; HideakiAACI TokyoAACO JPAAGP Fukuda; Hideaki Tokyo JP - A wafer-supporting device for supporting a wafer thereon adapted to be installed in a semiconductor-processing apparatus includes: a base surface; and protrusions protruding from the base surface and having rounded tips for supporting a wafer thereon. The rounded tips are such that a reverse side of a wafer is supported entirely by the rounded tips by point contact. The protrusions are disposed substantially uniformly on an area of the base surface over which a wafer is placed, wherein the number (N) and the height (H [μm]) of the protrusions as determined in use satisfy the following inequities per area for a 300-mm wafer: | 01-17-2013 |
20130115763 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 05-09-2013 |
20140017414 | Method for Forming Aluminum Oxide Film Using Al Compound Containing Alkyl Group and Alkoxy or Alkylamine Group - A method for forming a conformal film of aluminum oxide on a substrate having a patterned underlying layer by PEALD includes: adsorbing an Al precursor containing an Al—C bond and an Al—O—C or Al—N—C bond; providing an oxidizing gas and an inert gas; applying RF power to the reactant gas and the reaction-assisting gas to react the adsorbed precursor with the reactant gas on the surface, thereby forming a conformal film of aluminum oxide on the patterned underlying layer of the substrate, wherein the substrate is kept at a temperature of about 200° C. or lower. | 01-16-2014 |
20140273477 | Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES - Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). | 09-18-2014 |
20140273531 | Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES - Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). | 09-18-2014 |
20150017794 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 01-15-2015 |
20150056540 | Method of Forming Metal Oxide Hardmask - A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula Si | 02-26-2015 |