| Patent application number | Description | Published |
|---|
| 20080224222 | SEMICONDUCTOR DEVICE HAVING A FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV. | 09-18-2008 |
| 20080277743 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate electrode includes material having a second work function, wherein the second work function is higher than that of the spacers. | 11-13-2008 |
| 20090029539 | METHOD FOR FABRICATING TUNGSTEN LINE AND METHOD FOR FABRICATING GATE OF SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer. | 01-29-2009 |
| 20090032887 | TRANSISTOR HAVING GATE ELECTRODE WITH CONTROLLED WORK FUNCTION AND MEMORY DEVICE HAVING THE SAME - A transistor includes a gate insulation layer over a substrate, a gate line comprising electrodes each having a different work function on the gate insulation layer, and a source junction and a drain junction formed inside portions of the substrate on first and second sides of the gate line. | 02-05-2009 |
| 20090114981 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed. | 05-07-2009 |
| 20090115003 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a stacked layer including a tungsten layer, forming a hard mask pattern over the stacked layer, and oxidizing a surface of the hard mask pattern to form a stress buffer layer. A portion of the stacked layer uncovered by the hard mask pattern is removed using the hard mask pattern and the stress buffer layer as an etch mask, thereby forming a first resultant structure. A capping layer is formed over the first resultant structure, the capping layer is etched to retain the capping layer on sidewalls of the first resultant structure, and the remaining portion of the stacked layer uncovered by the hard mask pattern is removed. | 05-07-2009 |
| 20090117751 | METHOD FOR FORMING RADICAL OXIDE LAYER AND METHOD FOR FORMING DUAL GATE OXIDE LAYER USING THE SAME - A method for fabricating a radical oxide layer includes providing a substrate, forming an oxide layer over the substrate through a radical oxidation process, and performing a thermal treatment on the oxide layer by using oxygen (O | 05-07-2009 |
| 20090218616 | TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD FOR FABRICATING THE SAME - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar. | 09-03-2009 |
| 20090269917 | Method for manufacturing recess gate in a semiconductor device - A method for manufacturing a recess gate in a semiconductor device includes forming a field oxide layer on a substrate to define an active region, forming a hard mask pattern over the substrate to selectively expose at least a portion of the active region, forming a recess pattern in the active region through an etching process using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulating layer over the substrate, and forming a gate electrode over the gate insulating layer to cover at least the recess pattern. | 10-29-2009 |
| 20100084714 | DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL - A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region. | 04-08-2010 |
| 20100133619 | SEMICONDUCTOR DEVICE HAVING A FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV. | 06-03-2010 |
| 20100219466 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed. | 09-02-2010 |
| 20100308403 | TRANSISTOR HAVING VERTICAL CHANNEL - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar. | 12-09-2010 |
| 20110042760 | SEMICONDUCTOR DEVICE WITH GATE STRUCTURE - A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure. | 02-24-2011 |
| 20110068380 | SEMICONDUCTOR DEVICE WITH BULB-TYPE RECESSED CHANNEL AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers. | 03-24-2011 |
| 20110068393 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate electrode includes material having a second work function, wherein the second work function is higher than that of the spacers. | 03-24-2011 |
