Patent application number | Description | Published |
20080276042 | DATA STORAGE SYSTEM AND METHOD - Disclosed are a redundant data storage system (e.g., a RAID system) and a method of operating such a redundant data storage system that provides significant power savings with minimal reduction in reliability. The system and method allow up to half of the memory devices in any of the memory arrays in the system to be placed in standby without significantly impacting the read accesses. The system and method further designate reserved areas in the active memory devices as write-journals, which have at least the same level of protection as the main arrays. The write-journals allow data to be written without powering up a standby memory device. Thus, power consumption is minimized without impacting reliability. | 11-06-2008 |
20080276043 | DATA STORAGE SYSTEM AND METHOD - Disclosed are a redundant data storage system (e.g., a RAID system) and a method of operating such a redundant data storage system that provides significant power savings with minimal reduction in reliability. The system and method allow up to half of the memory devices in any of the memory arrays in the system to be placed in standby without significantly impacting the read accesses. The system and method further designate reserved areas in the active memory devices as write-journals, which have at least the same level of protection as the main arrays. The write-journals allow data to be written without powering up a standby memory device. Thus, power consumption is minimized without impacting reliability. | 11-06-2008 |
20080276124 | INCOMPLETE WRITE PROTECTION FOR DISK ARRAY - The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection level of the write logs is equal to or greater than the data protection level of the storage units. Moreover, the write logs have metadata describing contents of the write logs, wherein the metadata include a sequence number identifying the age of the metadata. Each of the data blocks is a member of a parity group having addressable data blocks and first parity blocks. The addressable data blocks have at least one host data block and at least one associated data block. | 11-06-2008 |
20080276146 | INCOMPLETE WRITE PROTECTION FOR DISK ARRAY - The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection level of the write logs is equal to or greater than the data protection level of the storage units. Moreover, the write logs have metadata describing contents of the write logs, wherein the metadata include a sequence number identifying the age of the metadata. Each of the data blocks is a member of a parity group having addressable data blocks and first parity blocks. The addressable data blocks have at least one host data block and at least one associated data block. | 11-06-2008 |
20120002895 | BITMAP COMPRESSION FOR FAST SEARCHES AND UPDATES - Bitmap compression for fast searches and updates is provided. Compressing a bitmap includes receiving a bitmap to compress, and reading the bitmap to determine a value of a bit location for all bits in the bitmap. In one embodiment, a compressed bitmap is created by encoding a variable number of bytes to represent a distance between adjacent 1s in the uncompressed bitmap. In another embodiment, a compressed bitmap is created by representing a distance between adjacent 1s in the uncompressed bitmap using a plurality of bits, and encoding a marker word to indicate the number of bits used to represent the distance. | 01-05-2012 |
20120173790 | STORAGE SYSTEM CACHE WITH FLASH MEMORY IN A RAID CONFIGURATION - Embodiments of the invention relate to a storage system cache with flash memory units organized in a RAID configuration. An aspect of the invention includes a storage system comprising a storage system cache with flash memory in a RAID configuration. The storage cache comprises flash memory units organized in an array configuration. Each of the flash memory units comprises flash memory devices and a flash unit controller. Each flash unit controller manages data access and data operations for its corresponding flash memory devices. The storage system further includes an array controller, coupled to the flash memory units, and that manages data access and data operations for the flash memory units and organizes data as full array stripes. The storage system further includes a primary storage device, which is coupled to the array controller, and stores data for the storage system. The storage system further includes a storage cache controller, coupled to the array controller, and comprises a block line manager that buffers write data to be cached for a write operation until the storage cache controller has accumulated an array band, and commits write data to the array controller as full array stripes. The storage cache controller receives storage commands from at least one host system. The storage cache controller determines for a write data storage command, whether to store write data in the storage cache and/or in the primary storage device; and for a read data storage command, whether to access read data from the storage cache or from the primary storage device. | 07-05-2012 |
20120221920 | MULTIPLE ERASURE CORRECTING CODES FOR STORAGE ARRAYS - Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe. | 08-30-2012 |
20120221926 | Nested Multiple Erasure Correcting Codes for Storage Arrays - Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to t | 08-30-2012 |
20120297113 | OPTIMIZED FLASH BASED CACHE MEMORY - Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold. | 11-22-2012 |
20120297127 | OPTIMIZED FLASH BASED CACHE MEMORY - Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold. | 11-22-2012 |
20120331367 | Nested Multiple Erasure Correcting Codes for Storage Arrays - Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to t | 12-27-2012 |
20130054873 | STORAGE SYSTEM CACHE USING FLASH MEMORY WITH DIRECT BLOCK ACCESS - Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks. | 02-28-2013 |
20130205168 | PARTIAL-MAXIMUM DISTANCE SEPARABLE (PMDS) ERASURE CORRECTING CODES FOR STORAGE ARRAYS - Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe. | 08-08-2013 |
20130205181 | PARTIAL-MAXIMUM DISTANCE SEPARABLE (PMDS) ERASURE CORRECTING CODES FOR STORAGE ARRAYS - Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices. | 08-08-2013 |
20140129762 | SKEWING EXPECTED WEAROUT TIMES OF MEMORY DEVICES - Aspects of the present invention include a system, method, and computer program product for skewing expected wearout times of memory devices in an array are provided according to some embodiments of the present invention. In general, the method includes determining or receiving an amount of spare space to provide in an array of memory devices, allocating the spare space non-uniformly to the memory devices in the array, and skewing expected wearout times of the memory devices by controlling writing of data to the array according to the allocation of the spare space. | 05-08-2014 |
20140211602 | HIGH DENSITY HYBRID STORAGE SYSTEM - A system includes a linear storage media tier; a second storage tier having higher performance than the linear storage media tier; a data controller for moving data between the tiers; and a host interface responsive to disk and/or network storage commands. The linear storage media tier includes: a rest area for storing reels having linear media thereon, at least one linear media drive configured for reading and/or writing the linear media, and at least one robot for transporting the linear storage media between the rest area and the at least one linear media drive. The robot moves along a first surface via contact with the surface. A system according to another embodiment includes a linear storage media tier characterized by having a read access time to any block of data stored on any reel in the rest area in less than 10 seconds. | 07-31-2014 |
Patent application number | Description | Published |
20080276041 | DATA STORAGE ARRAY SCALING METHOD AND SYSTEM WITH MINIMAL DATA MOVEMENT - A method for rearranging data blocks in a data storage system when adding new storage devices to create an expanded data storage system. A temporary configuration is selected for which the exchange of one or more data blocks between the temporary configuration and the source configuration produces the destination configuration before identifying and exchanging data blocks between the temporary configuration and the source configuration to produce the destination configuration. A single data element transfer chain embodiment provides superior performance in an embodiment that maintains (does not reduce) the source array data storage efficiency at the destination array after scaling. When adding a single new device to an existing array, the required data movement is minimized and does not exceed the capacity of the new device. | 11-06-2008 |
20080276057 | DATA STORAGE ARRAY SCALING METHOD AND SYSTEM WITH MINIMAL DATA MOVEMENT - A method for rearranging data blocks in a data storage system when adding new storage devices to create an expanded data storage system. A temporary configuration is selected for which the exchange of one or more data blocks between the temporary configuration and the source configuration produces the destination configuration before identifying and exchanging data blocks between the temporary configuration and the source configuration to produce the destination configuration. A single data element transfer chain embodiment provides superior performance in an embodiment that maintains (does not reduce) the source array data storage efficiency at the destination array after scaling. When adding a single new device to an existing array, the required data movement is minimized and does not exceed the capacity of the new device. | 11-06-2008 |
20090132890 | Anamorphic Codes - The error tolerance of an array of m storage units is increased by using a technique referred to as “dodging.” A plurality of k stripes are stored across the array of storage units in which each stripe has n+r elements that correspond to a symmetric code having a minimum Hamming distance d=r+1. Each respective element of a stripe is stored on a different storage unit. An element is selected when a difference between a minimum distance of the donor stripe and a minimum distance of a recipient stripe is greater or equal to 2. The selected element is also stored on a storage unit having no elements of the recipient stripe. A lost element of the recipient stripe is then rebuilt on the selected element. | 05-21-2009 |
20100262792 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ESTIMATING WHEN A RELIABLE LIFE OF A MEMORY DEVICE HAVING FINITE ENDURANCE AND/OR RETENTION, OR PORTION THEREOF, WILL BE EXPENDED - A method according to one embodiment includes gathering monitor data information from a memory device having finite endurance and/or retention, the monitor data being data of known content stored in dedicated memory cells of known write cycle count; analyzing the monitor data information; estimating a reliable life of the memory device or portion thereof based on the analysis; tracking a rate of change of at least a highest cycle count of user data; estimating when the reliable life of the memory device or portion thereof will be expended based on the tracking and the estimating; and taking an action prior to the reliable life of the memory device or portion thereof being expended. Additional systems, methods, and computer program products are also disclosed. | 10-14-2010 |
20100262793 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SKEWING EXPECTED WEAROUT TIMES OF MEMORY DEVICES - A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the memory array at a second number of writes per unit time; and skewing expected wearout times of the memory devices by making the second number of writes per unit time less than the first number of writes per unit time. A method in another embodiment includes writing first data to a first memory device of a memory array; writing second data to a second memory device of the memory array; and skewing expected wearout times of the memory devices by making a number of available storage units cm the second memory device less than a number of available storage units on the first memory device. | 10-14-2010 |
20100262795 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING MONITOR DATA INFORMATION FROM A PLURALITY OF MEMORY DEVICES HAVING FINITE ENDURANCE AND/OR RETENTION - A method according to one embodiment includes gathering monitor data information from a plurality of memory devices having finite endurance and/or retention, the monitor data being data of known content stored in dedicated memory cells of known write cycle count; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed. | 10-14-2010 |
20100262875 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A RETENTION BEHAVIOR FOR AT LEAST ONE BLOCK OF A MEMORY DEVICE HAVING FINITE ENDURANCE AND/OR RETENTION - A method according to one embodiment includes writing monitor data to at least one block of a memory device having finite endurance and/or retention; reading the monitor data after a period of time; determining a retention behavior of the at least one block based on the reading; and outputting a result of the determining. A memory device according to one embodiment includes a plurality of memory blocks having finite endurance and/or retention, at least one of the blocks having monitor data written therein; and circuitry for addressing the blocks. A system according to one embodiment includes a memory device having finite endurance and/or retention, the memory device comprising: a plurality of memory blocks, at least one of the blocks having monitor data written therein, wherein the at least one block has been written to a plurality of times prior to writing the monitor data; and circuitry for addressing the blocks. | 10-14-2010 |
20130013968 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING MONITOR DATA INFORMATION FROM A PLURALITY OF MEMORY DEVICES HAVING FINITE ENDURANCE AND/OR RETENTION - A method according to one embodiment includes gathering information about monitor data from a plurality of memory devices having finite endurance and/or retention, the monitor data being (i) data of known content stored in dedicated memory cells of known write cycle count, and (ii) write protected for preventing the monitor data from being overwritten with user data; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed. | 01-10-2013 |