Patent application number | Description | Published |
20090024977 | LOCAL PREFERRED DIRECTION ARCHITECTURE, TOOLS, AND APPARATUS - model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout. | 01-22-2009 |
20090089735 | METHOD AND APPARATUS FOR ROUTING - Some embodiments of the invention provide a routing method. The routing method receives a set of nets to route in a region of an integrated circuit (“IC”) layout. The routing method defines routes for the nets in a manner that ensures that each segment of each route is not less than a minimum length that is required for the segment. | 04-02-2009 |
20090106710 | METHOD AND APPARATUS FOR SYNTHESIS - Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks. | 04-23-2009 |
20100180250 | METHOD AND APPARATUS FOR GENERATING LAYOUT REGIONS WITH LOCAL PREFERRED DIRECTIONS - Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiring directions to at least two of the regions. In some embodiments, the method decomposing the first wiring layer by using the vertices of items in the layout to decompose the layout. In some of these embodiments, the items include macro blocks. The method of some embodiments also identifies several power via arrays on the first wiring layer, and identifies a local preferred wiring direction based on the arrangement of the power via arrays on the first wiring layer. | 07-15-2010 |
Patent application number | Description | Published |
20080203581 | INTEGRATED CIRCUIT - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal path being coupled to the first signal path, and a second substrate on the second interface layer. In one embodiment, the second substrate includes an electronic device, the electronic device being coupled to the second signal path of the second interface layer. | 08-28-2008 |
20100032817 | SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE MOLDING COMPOUND, SEMICONDUCTOR CHIP AND LEADFRAME AND METHOD FOR PRODUCING THE SAME - A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device. | 02-11-2010 |
20110162204 | INTEGRATED DEVICE - An integrated device is disclosed. In one embodiment, the integrated device includes a carrier substrate with a through hole and a contact sleeve. A circuit chip is provided with a contact pad above the carrier substrate. A conductive material electrically connects the contact pad to the contact sleeve. | 07-07-2011 |
Patent application number | Description | Published |
20090008796 | COPPER ON ORGANIC SOLDERABILITY PRESERVATIVE (OSP) INTERCONNECT - Provided is a semiconductor package, and a method for constructing the same, including a first substrate, a first semiconductor chip attached to the first substrate, and a first copper wire. At least one of the first substrate and the first semiconductor chip has an Organic Solderability Preservative (OSP) material coated on at least a portion of one surface, and the first copper wire is wire bonded through the OSP material to the first substrate and the first semiconductor chip. | 01-08-2009 |
20090194871 | SEMICONDUCTOR PACKAGE AND METHOD OF ATTACHING SEMICONDUCTOR DIES TO SUBSTRATES - A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds. | 08-06-2009 |
20120034738 | SEMICONDUCTOR PACKAGE AND METHOD OF ATTACHING SEMICONDUCTOR DIES TO SUBSTRATES - A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds. | 02-09-2012 |