Patent application number | Description | Published |
20110312151 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 12-22-2011 |
20120012806 | IMPROVED ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD - This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying at lease the top surface region of the switching element such that the conductive material is in direct contact with the switching element. The side wall spacer reduces a contact area for the switching element and the conductive material and thus a reduced active device area for the switching device. In a specific embodiment, the reduced area provides for an increase in device ON/OFF current ratio. | 01-19-2012 |
20120015506 | TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process. | 01-19-2012 |
20120043520 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction. | 02-23-2012 |
20120043621 | STACKABLE NON-VOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND METHOD - A method for forming a vertically stacked memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first plurality of memory cells are formed overlying the first dielectric material. Each of the first plurality of memory cells includes at least a first top metal wiring structure spatially extending in a first direction, a first bottom wiring structure spatially extending in a second direction orthogonal to the first top metal wiring structure, and a first switching element sandwiched in an intersection region between the first top metal wiring structure and the first bottom metal wiring structure. In a specific embodiment, the method forms a thickness of second dielectric material overlying the first plurality of memory. A second plurality of memory cells are formed overlying the second dielectric material. Each of the second plurality of memory cells includes at least a second top metal wiring structure extending in the first direction, a second bottom wiring structure arranged spatially orthogonal to the second top metal wiring structure, and a second switching element sandwiched in an intersection region of the second top metal wiring structure and the second bottom metal wiring structure. | 02-23-2012 |
20120108030 | METHOD FOR OBTAINING SMOOTH, CONTINUOUS SILVER FILM - A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide. | 05-03-2012 |
20120112155 | INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate. A second bottom wiring material is formed overlying the second thickness of dielectric material and filling the opening region to form a vertical interconnect structure in the first peripheral region. A second bottom wiring structure is formed from the second wiring material for a second array of devices. The second bottom wiring structure is separated from the first bottom wiring structure by at least the second thickness of dielectric material and spatially configured to extend in the first direction. The first wiring structure and the second wiring structure are electrically connected by the vertical interconnect structure in the first peripheral region to a control circuitry on the substrate. | 05-10-2012 |
20120142163 | P+ POLYSILICON MATERIAL ON ALUMINUM FOR NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element. | 06-07-2012 |
20120187364 | ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD - A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element. | 07-26-2012 |
20120220100 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 08-30-2012 |
20120252183 | METHOD FOR OBTAINING SMOOTH, CONTINUOUS SILVER FILM - A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide. | 10-04-2012 |
20120273748 | INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure. | 11-01-2012 |
20120305874 | Vertical Diodes for Non-Volatile Memory Device - A steering device. The steering device includes an n-type impurity region comprising a zinc oxide material and a p-type impurity region comprising a silicon germanium material. A pn junction region formed from the zinc oxide material and the silicon germanium material. The steering device is a serially coupled to a resistive switching device to provide rectification for the resistive switching device to form a non-volatile memory device. | 12-06-2012 |
20120309188 | METHOD TO IMPROVE ADHESION FOR A SILVER FILLED OXIDE VIA FOR A NON-VOLATILE MEMORY DEVICE - A method for forming an interconnect structure for a memory device. The method includes providing a partially fabricated device. The partially fabricated device includes a switching element overlying a first wiring structure. A thickness of dielectric material is deposited overlying the first wiring structure. The method deposits an adhesion material overlying the thickness of the dielectric material. A via opening is formed in a portion of the thickness of the dielectric material to expose a surface region of the switching element while the adhesion material is maintained overlying the dielectric material. A second wiring material is deposited overlying the thickness of the dielectric material and to fill at least part of the via opening and forming a thickness of second wiring material overlying the adhesion material. The adhesion material maintains the second wiring material to be adhered to the surface region of the thickness of the dielectric material. | 12-06-2012 |
20130020548 | SEED LAYER FOR A P+ SILICON GERMANIUM MATERIAL FOR A NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material. | 01-24-2013 |
20130075689 | STACKABLE NON-VOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND METHOD - A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8. | 03-28-2013 |
20130119510 | DEVICES INCLUDING A P-I-N DIODE DISPOSED ADJACENT A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL - A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO | 05-16-2013 |
20130121061 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided. | 05-16-2013 |
20130134419 | VERTICAL DIODES FOR NON-VOLATILE MEMORY DEVICE - A steering device. The steering device includes an n-type impurity region comprising a zinc oxide material and a p-type impurity region comprising a silicon germanium material. A pn junction region formed from the zinc oxide material and the silicon germanium material. The steering device is a serially coupled to a resistive switching device to provide rectification for the resistive switching device to form a non-volatile memory device. | 05-30-2013 |
20130157457 | INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure. | 06-20-2013 |
20130164921 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided. | 06-27-2013 |
20130214241 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction. | 08-22-2013 |
20130228738 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided. | 09-05-2013 |
20130234092 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and overlies the amorphous silicon material and connected to a common bitline. | 09-12-2013 |
20130234104 | MEMORY CELL THAT INCLUDES A SIDEWALL COLLAR FOR PILLAR ISOLATION AND METHODS OF FORMING THE SAME - A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided. | 09-12-2013 |
20130286728 | NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. Numerous other aspects are provided. | 10-31-2013 |
20130313505 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - A memory cell is provided that includes a semiconductor pillar and a reversible resistance-switching element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region includes a first proportion of germanium greater than a proportion of germanium in the top region and/or the bottom region. The reversible resistivity-switching element includes a material selected from the group consisting of NiO, Nb | 11-28-2013 |
20140110660 | NONVOLATILE MEMORY CELL WITHOUT A DIELECTRIC ANTIFUSE HAVING HIGH- AND LOW-IMPEDANCE STATES - A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another. | 04-24-2014 |
20140117307 | Nanowire Sized Opto-Electronic Structure and Method for Modifying Selected Portions of Same - A method for treating a LED structure with a substance, the LED structure includes an array of nanowires on a planar support. The method includes producing the substance at a source and causing it to move to the array along a line. The angle between the line followed by the substance and the plane of the support is less than 90° when measured from the center of the support. The substance is capable of rendering a portion of the nanowires nonconductive or less conductive compared to before being treated by the substance. | 05-01-2014 |
20140117401 | Nanowire LED Structure and Method for Manufacturing the Same - A method for ablating a first area of a light emitting diode (LED) device which includes an array of nanowires on a support with a laser is provided. The laser ablation exposes a conductive layer of the support that is electrically connected to a first conductivity type semiconductor nanowire core in the nanowires, to form a first electrode for the LED device. In embodiments, the nanowires are aligned at least 20 degrees from the plane of the support. A light emitting diode (LED) structure includes a first electrode for contacting a first conductivity type nanowire core, and a second electrode for contacting a second conductivity type shell enclosing the nanowire core, where the first electrode and/or at least a portion of the second electrode are flat. | 05-01-2014 |
20140127876 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 05-08-2014 |
20140158975 | MEMORY CELL THAT INCLUDES A SIDEWALL COLLAR FOR PILLAR ISOLATION AND METHODS OF FORMING THE SAME - A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided. | 06-12-2014 |
20140166968 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided. | 06-19-2014 |
20140217353 | STACKABLE NON-VOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND METHOD - A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8. | 08-07-2014 |
20140217354 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A monolithic three-dimensional memory array is provided that includes a first memory level and a second memory level disposed above or below the first memory level. The first memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped p type region. The second memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped n type region. Numerous other aspects are also provided. | 08-07-2014 |
20140241031 | DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided. | 08-28-2014 |
20140264242 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A disturb-resistant nonvolatile memory device includes a substrate, a dielectric material overlying the semiconductor substrate, a first cell comprising a first wiring structure extending in a first direction overlying the dielectric material, a first contact region, a first resistive switching media, and a second wiring structure extending in a second direction orthogonal to the first direction, a second cell comprising the first wiring structure, a second contact region, a second resistive switching media, and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure, and a dielectric material disposed at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region. | 09-18-2014 |
20140284551 | Nanowire LED Structure with Decreased Leakage and Method of Making Same - A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores located over a support, and an insulating mask layer located over the support. The nanowire cores include semiconductor nanowires epitaxially extending from portions of a semiconductor surface of the support exposed through openings in the insulating mask layer. The device also includes a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores, a first electrode layer that contacts the second conductivity type semiconductor shells and extends into spaces between the semiconductor shells, and an insulating layer located between the insulating mask layer and the first electrode in the spaces between the semiconductor shells. | 09-25-2014 |
20140319450 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE USING VIA-FILL AND ETCHBACK TECHNIQUE - A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material. | 10-30-2014 |
20140346427 | SELECTIVE DEPOSITION OF SILVER FOR NON-VOLATILE MEMORY DEVICE FABRICATION - A method of forming a non-volatile memory device includes providing a semiconductor substrate having a surface region, thereafter forming a first dielectric layer overlying, thereafter forming a first wiring material, thereafter forming amorphous silicon layer, and patterning and etching these layers to form first structures extending in a first direction and having a switching element. Thereafter, a method may include depositing a second dielectric layer overlying the first structures and having a dielectric surface region, forming an opening region in the second dielectric material to exposing part of the switching element, and depositing a silver material in the opening region, but not on the dielectric surface region. | 11-27-2014 |
20140346432 | ON/OFF RATIO FOR NONVOLATILE MEMORY DEVICE AND METHOD - A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element. | 11-27-2014 |
20140361244 | Nanowire LED Structure with Decreased Leakage and Method of Making Same - A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores located over a support and extending from portions of a semiconductor surface of the support exposed through openings in the insulating mask layer, and a plurality of semiconductor shells extending over the respective nanowire cores. Each of the plurality of semiconductor shells includes at least one semiconductor interior shell extending around the respective one of the plurality nanowire cores, and a second conductivity type semiconductor outer shell extending around the at least one semiconductor interior shell. A first electrode layer contacts the second conductivity type semiconductor outer shell of the plurality of semiconductor shells and extends into spaces between the semiconductor shells. The semiconductor interior shell includes a semiconductor foot portion which extends under the first electrode and under the respective second conductivity type semiconductor outer shell on the insulating masking layer in the spaces between the plurality of semiconductor shells. | 12-11-2014 |
20140367638 | Insulating Layer for Planarization and Definition of the Active Region of a Nanowire Device - Various embodiments include methods of fabricating a semiconductor device that include forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core, forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface, removing a portion of the insulating material layer to define an active region of nanowires, and forming an electrical contact over the substantially planar top surface of the insulating material layer. | 12-18-2014 |
20150144968 | METHOD OF STRESS INDUCED CLEAVING OF SEMICONDUCTOR DEVICES - A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves. | 05-28-2015 |
20150179894 | METHODS OF LOCATING DIFFERENTLY SHAPED OR DIFFERENTLY SIZED LED DIE IN A SUBMOUNT - Methods of locating a plurality of light emitting diode (LED) dies in a submount include providing the plurality of LED dies across a surface of the submount, the submount including a plurality of tubs corresponding in shape and/or size with the shape and/or size of the LED dies to fill each tub with correspondingly shaped and/or sized LED die. | 06-25-2015 |
20150179895 | LED SUBMOUNT WITH INTEGRATED INTERCONNECTS - A submount for light emitting diode (LED) die includes a substrate containing a plurality of tubs configured to receive an LED die, and a plurality of integrated interconnects integrated into the substrate. At least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount. | 06-25-2015 |
20150188051 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline. | 07-02-2015 |
20150200362 | TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A semiconductor device having a memory device includes a semiconductor substrate, a first dielectric layer disposed above the semiconductor substrate, a first adhesion layer disposed upon the first dielectric layer, a bottom wiring metal disposed upon the first adhesion layer, a first barrier layer disposed upon the bottom wiring metal, a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions, a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles, a second barrier layer disposed upon the conductive metal material, a top wiring metal disposed upon the second barrier layer, and wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material. | 07-16-2015 |
20150214439 | LED DEVICE WITH BRAGG REFLECTOR AND METHOD OF SINGULATING LED WAFER SUBSTRATES INTO DICE WITH SAME - A method of dicing semiconductor devices from a substrate includes forming a Bragg reflector over a bottom side of the substrate, where the bottom side is opposite of a top side, generating a pattern of defects in the substrate with a laser beam from the bottom side of the substrate, and applying pressure to the substrate to dice the substrate along the pattern of defects. The Bragg reflector includes a first layer of dielectric material having a first index of refraction and a second dielectric material having a second index of refraction different from the first index of refraction. | 07-30-2015 |
20150263237 | NANOWIRE LED STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for ablating a first area of a light emitting diode (LED) device which includes an array of nanowires on a support with a laser is provided. The laser ablation exposes a conductive layer of the support that is electrically connected to a first conductivity type semiconductor nanowire core in the nanowires, to form a first electrode for the LED device. In embodiments, the nanowires are aligned at least 20 degrees from the plane of the support. A light emitting diode (LED) structure includes a first electrode for contacting a first conductivity type nanowire core, and a second electrode for contacting a second conductivity type shell enclosing the nanowire core, where the first electrode and/or at least a portion of the second electrode are flat. | 09-17-2015 |
20150325310 | DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME - A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current. | 11-12-2015 |