| Patent application number | Description | Published |
|---|
| 20080258308 | Method of controlled low-k via etch for Cu interconnections - An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer. | 10-23-2008 |
| 20080290448 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 11-27-2008 |
| 20090087992 | METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRENCH REACTIVE ION ETCHING IN A VIA FIRST SCHEME - A method of minimizing undercut of a hard mask in an integrated circuit (IC) structure including steps of providing an IC structure having a substrate, a interlayer dielectric layer, and a hard mask, forming a via in said IC structure, and depositing an organic planarizing layer (OPL) over the IC structure such that it fills the vias formed therein. The method also includes steps of forming a masking structure layer over the OPL, forming an opening in the masking structure that has a critical dimension (CD) smaller than an opening design dimension, anisotropic etching the OPL such that sidewall of the via remains covered with the OPL while forming a trench, and removing any remaining OPL on the sidewalls and trench, wherein the undercut of the sidewalls with respect to the hard mask is minimized by the covering of OPL during the anisotropic etching process. | 04-02-2009 |
| 20090203192 | Crack Stop Trenches - Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels. | 08-13-2009 |
| 20090239375 | Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 09-24-2009 |
| 20100032841 | Semiconductor Devices and Structures Thereof - A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region. | 02-11-2010 |
| 20100144112 | Methods of Manufacturing Semiconductor Devices - Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region. | 06-10-2010 |
| 20100197112 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 08-05-2010 |
| 20110074033 | Crack Stop Trenches - Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels. | 03-31-2011 |
