Patent application number | Description | Published |
20100266277 | DATA TRANSMISSION USING DIRECT AND INDIRECT OPTICAL PATHS - A system for transmitting data, including: a transmitter node having a setup path packet and multiple data packets; a receiver node connected to the transmitter node by a first optical channel (OC); and a first intermediate node having a first forwarding module and connected to the transmitter node by a second OC and to the receiver node by a third OC, where the transmitter node transmits the setup path packet and a first subset of the multiple data packets to the first intermediate node using the second OC, where the first forwarding module relays, in response to receiving the setup packet, the first subset to the receiver node by switching the first subset from the second OC to the third OC, and where the receiver node receives a second subset of the multiple data packets from the transmitter node using the first OC. | 10-21-2010 |
20110082965 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 04-07-2011 |
20110093646 | PROCESSOR-BUS ATTACHED FLASH MAIN-MEMORY MODULE - A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the address to a cache line in a cache memory associated with a remote processor, and sending a coherency message from the module to the remote processor to change a state of the cache line in the cache memory. The method further includes receiving, at the module, the cache line from the remote processor, sending, using processor bus and in response to the read request, the cache line to the requesting processor, identifying a requested page stored within the flash memory based on the address, storing a copy of the requested page in the memory buffer, and writing the cache line to the copy of the requested page. | 04-21-2011 |
20110103397 | TWO-PHASE ARBITRATION MECHANISM FOR A SHARED OPTICAL LINKS - A method for arbitration in an arbitration domain. The method includes: receiving, by each node of a plurality of nodes in the arbitration domain, an arbitration request from each sending node of the plurality of nodes in the arbitration domain, where the plurality of nodes in the arbitration domain each use a shared data channel to send data to a set of receiving nodes; assigning, by each node in the arbitration domain, consecutive time slots to each sending node based on a plurality of priorities assigned to the plurality of nodes in the arbitration domain; for each time slot: sending, from the arbitration domain, a switch request to a receiving node designated by the sending node, where the receiving node is in the set of receiving nodes; and sending, by the sending node, data to the receiving node via the shared data channel during the time slot. | 05-05-2011 |
20110179208 | TIME DIVISION MULTIPLEXING BASED ARBITRATION FOR SHARED OPTICAL LINKS - A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel. | 07-21-2011 |
20120110251 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 05-03-2012 |
20130145086 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address. | 06-06-2013 |
20160043977 | DATA DEDUPLICATION AT THE NETWORK INTERFACES - A method for data deduplication during execution of an application on a plurality of computing nodes, including: generating, by a first processor in a first computing node executing the application, a first message to process application data owned by a second computing node executing the application; receiving, by a first network interface (NI) of the first computing node, the first message; extracting, by the first NI, a first key from the first message; determining, by the first NI, the first key is not a duplicate; and placing, by the first NI and in response to the first key not being a duplicate, the first message on a network connecting the first computing node to the second computing node. | 02-11-2016 |