| Patent application number | Description | Published |
|---|
| 20090131009 | RECEIVED COMMUNICATION SIGNAL PROCESSING METHODS AND COMPONENTS FOR WIRELESS COMMUNICATION EQUIPMENT - A wireless transmit receive unit (WTRU) and methods are used in a wireless communication system to process sampled received signals to establish and/or maintain wireless communications. A selectively controllable coherent accumulation unit produces power delay profiles (PDPs). A selectively controllable post processing unit passes threshold qualified magnitude approximation values and PDP positions to a device such as a rake receiver to determine receive signal paths. | 05-21-2009 |
| 20090158008 | SOFTWARE PARAMETERIZABLE CONTROL BLOCKS FOR USE IN PHYSICAL LAYER PROCESSING - A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode. | 06-18-2009 |
| 20090203409 | UMTS FDD MODEM OPTIMIZED FOR HIGH DATA RATE APPLICATIONS - A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators. | 08-13-2009 |
| 20090238124 | METHOD AND APPARATUS FOR COMBINED MEDIUM ACCESS CONTROL AND RADIO LINK CONTROL PROCESSING - A method and apparatus for combined medium access control (MAC) and radio link control (RLC) processing are disclosed. For uplink processing, a combined MAC/RLC (CMR) entity generates an SDU descriptor and allocates protocol data unit (PDU) descriptor resources. A protocol engine (PE) populates a PDU descriptor for each PDU carrying at least a portion of the SDU and generates a MAC PDU in a physical layer shared memory based on the SDU descriptor and the PDU descriptor. The MAC PDU is generated while moving RLC SDU data from the bulk memory to the physical layer shared memory. For downlink processing, received MAC PDUs are stored in the physical layer shared memory. The PE reads MAC and RLC headers in the MAC PDU and populates an SDU segment descriptor (SD) and corresponding PDU descriptors for each SDU segment. The CMR entity merges SDU SDs that comprise a same RLC SDU. | 09-24-2009 |
| 20090274248 | METHOD AND APPARATUS FOR CONTENTION-FREE INTERLEAVING USING A SINGLE MEMORY - A method and apparatus for contention free interleaving are disclosed. A single memory configured to use an address scheme wherein the most significant bits (MSBs) indicate which word in memory stores an interleaved piece of data. The least significant bits (LSBs) are used to calculate an index that identifies a specific soft-in/soft-out (SISO) decoder associated with a sub-word of the retrieved data. Using an interleaved address generator, the extrinsic data may be written into the memory in sequential order, but read out from the memory in interleaved order, effectively de-interleaving the data so it may be decoded. The generated interleaved address is used by SISO selector circuit which controls a multiplexer that routes the sub-word to its appropriate SISO decoder. The same address generator may be used to write interleaved extrinsic data from SISOs by reordering the sub-words, allowing the extrinsic data to be read in sequential order. | 11-05-2009 |
| 20100088529 | Data-Mover Controller With Plural Registers For Supporting Ciphering Operations - A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”. | 04-08-2010 |
| 20110158197 | METHOD AND APPARATUS FOR EFFICIENT OPERATION OF AN ENHANCED DEDICATED CHANNEL - A method for processing enhanced dedicated channel (E-DCH) data in a wireless transmit/receive unit (WTRU) includes sending two messages. A first message is sent from a physical layer to a medium access control (MAC) layer, and triggers MAC layer processing of E-DCH data. A second message is sent from the MAC layer to the physical layer, and enables the physical layer to compute control parameters for physical layer processing of the E-DCH data before the MAC layer processing of the E-DCH data is completed. | 06-30-2011 |
