| Patent application number | Description | Published |
|---|
| 20080204135 | METHOD AND SYSTEM FOR LOW NOISE AMPLIFIER (LNA) GAIN ADJUSTMENT THROUGH NARROWBAND RECEIVED SIGNAL STRENGTH INDICATOR (NRSSI) - A method for processing a plurality of signals may include amplifying an input signal and generating a wideband signal from the amplified input signal. The method may further include bandpass filtering the generated wideband signal to generate a narrowband signal, and adjusting amplification of the input signal based on a narrowband received signal strength indication of the generated narrowband signal, and/or a wideband received signal strength indication of the generated wideband signal. The amplified input signal may be downconverted to generate the wideband signal. The amplified input signal may be downconverted to an intermediate frequency (IF) and/or to a baseband signal to generate the wideband signal. At least one blocker signal may be bandpass filtered from the amplified input signal. | 08-28-2008 |
| 20090016466 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection - A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal. | 01-15-2009 |
| 20090130998 | ARCHITECTURAL TECHNIQUES FOR ENVELOPE AND PHASE SIGNAL ALIGNMENT IN RF POLAR TRANSMITTERS USING POWER AMPLIFIER FEEDBACK - In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly. | 05-21-2009 |
| 20090154598 | DIGITAL MODULATOR FOR A GSM/GPRS/EDGE WIRELESS PLAR RF TRANSMITTER - A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements. | 06-18-2009 |
| 20090168863 | POLAR TRANSMITTER WITH DIGITAL AND ANALOG FILTERING OF ENVELOPE - A calibration circuit measures the variation in a filter resistor within the analog domain of the envelope path of a polar transmitter and produces a digital value representative of that variation. A digital processor determines a digital control signal from the digital value that is used to compensate, in the digital domain of the envelope path, for the variation in the filter resistor in the analog domain. | 07-02-2009 |
| 20090268845 | RADIO TRANSMITTER INCORPORATING DIGITAL MODULATOR AND CIRCUITRY TO ACCOMMODATE BASEBAND PROCESSOR WITH ANALOG INTERFACE - A circuit provides a digital signal at optimal times to a digital processor of a transmitter. The circuit includes a complex analog-to-digital converter (ADC), a demodulator and a timing recovery circuit. The complex ADC is connected to receive an analog complex modulated baseband signal and to convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. The demodulator operates to demodulate the digital signal to produce a demodulated digital signal for input to the digital processor. The timing recovery circuit receives a control signal and activates the digital processor based on a fixed timing relationship between receipt of the control signal at the timing recovery circuit and receipt of the analog complex modulated baseband signal at the complex ADC. | 10-29-2009 |
| 20090268847 | PHASE LOCKED LOOP MODULATOR CALIBRATION TECHNIQUES - A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset. | 10-29-2009 |
| 20090274244 | DIGITAL DELAY ELEMENT FOR DELAY MISMATCH CANCELLATION IN WIRELESS POLAR TRANSMITTERS - A circuit and method therefor provides programmable digital delay that is produced to introduces a delay in either an envelope or a phase signal path of an RF polar transmitter in order to eliminate the delay mismatch between the two paths. For two signal paths, a faster signal may be delayed by a digital processor or a slower signal may be transmitted early so that signals in the two signal paths arrive at a specified circuit node in synchronization. Timing shift may be implemented in either the envelope signal path or the phase signal path and may be used to reduce or increase the timing of a signal path. | 11-05-2009 |
| 20090278613 | Two-point modulation polar transmitter architecture and method for performance enhancement - A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth. | 11-12-2009 |
| 20090289826 | TECHNIQUE FOR IMPROVING MODULATION PERFORMANCE OF TRANSLATIONAL LOOP RF TRANSMITTERS - A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop. | 11-26-2009 |
| 20090311978 | RF transceiver incorporating dual-use PLL frequency synthesizer - A frequency synthesizer for use in a transmitter operates to receive outbound transmit data and to modulate the outbound transmit data to produce a modulated RF signal. The modulated RF signal can then be amplified to produce an outbound RF signal. | 12-17-2009 |
| 20100120387 | CHANNEL-SELECT DECIMATION FILTER WITH PROGRAMMABLE BANDWIDTH - A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes. | 05-13-2010 |
| 20100290562 | Digital Compensation for Nonlinearities in a Polar Transmitter - A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal. | 11-18-2010 |
