| Patent application number | Description | Published |
|---|
| 20080228964 | Hybrid flex-and-board memory interconnect system - A hybrid memory interconnect system involving flexible cable and board interconnects is provided for improved memory bandwidth and power efficiency performance. To this purpose, signals between a microprocessor chip and one or more memory chips are routed via separate conductive paths, e.g. flexible cable for high-speed signals and conventional board interconnects for low-speed signals. The memory chips may be connected to a flexible cable and a supporting printed circuit board in various ways. | 09-18-2008 |
| 20090001528 | Lowering resistance in a coreless package - In one embodiment, the present invention includes a coreless substrate to provide a power net connection and a ground net connection to a semiconductor die, which is electrically coupled to the substrate, and a stiffener surrounding the semiconductor die and electrically coupled to the substrate to provide a lateral current path to the semiconductor die. Other embodiments are described and claimed. | 01-01-2009 |
| 20090162005 | Wafer based optical interconnect - In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter. | 06-25-2009 |
| 20090201113 | INTEGRATED INDUCTOR STRUCTURE AND METHOD OF FABRICATION - An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section. | 08-13-2009 |
| 20090244873 | OPTICAL PACKAGE - A method for aligning at least two photonic components over an interposer, and an optical package that may align such components. The method may include providing an interposer; fabricating electrical conductors passing from one surface of the interposer to an opposite surface of the interposer at selected contact positions; soldering the photonic components over the selected contact positions on the first surface, while allowing solder self-alignment. Other embodiments are described and claimed. | 10-01-2009 |
| 20100002398 | Multimode signaling on decoupled input/output and power channels - A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point. | 01-07-2010 |
| 20100078781 | INPUT/OUTPUT PACKAGE ARCHITECTURES, AND METHODS OF USING SAME - A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s. | 04-01-2010 |
| 20100096743 | Input/output package architectures, and methods of using same - A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s. | 04-22-2010 |
| 20100327424 | Multi-chip package and method of providing die-to-die interconnects in same - A multi-chip package includes a substrate ( | 12-30-2010 |
| 20110019386 | Multimode Signaling on Decoupled Input/Output and Power Channels - A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point. | 01-27-2011 |
