Patent application number | Description | Published |
20090063074 | Mask Haze Early Detection - Detecting haze formation on a mask by obtaining an optical property of the mask and determining progress of the haze formation based on the obtained optical property. | 03-05-2009 |
20100219175 | ROTATABLE PLATE AND HEATING/COOLING ELEMENT IN PROXIMITY THERETO - An apparatus for selectively heating/cooling one or more substrates and establishing an approximately uniform temperature in the one or more substrates during a heating or cooling event is described. In one embodiment, the apparatus comprises a rotatable hot/cold plate onto which the one or more substrates are placed and a heating/cooling element disposed in close proximity to the rotatable hot/cold plate for selectively elevating/lowering the temperature of the one or more substrates. | 09-02-2010 |
20100285399 | WAFER EDGE EXPOSURE UNIT - A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously. | 11-11-2010 |
20110024924 | METHOD AND STRUCTURE OF STACKING SCATTEROMETRY-BASED OVERLAY OR CD MARKS FOR MARK FOOTPRINT REDUCTION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch. | 02-03-2011 |
20110076843 | LITHOGRAPHY PATTERNING METHOD - A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer. | 03-31-2011 |
20120045192 | SYSTEM AND METHOD FOR IMPROVING IMMERSION SCANNER OVERLAY PERFORMANCE - System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner comprising a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method comprises providing a water tank at at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level. | 02-23-2012 |
20120168751 | Integrated Circuit Test Units with Integrated Physical and Electrical Test Regions - A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region. | 07-05-2012 |
20130032712 | OVERLAY ALIGNMENT MARK AND METHOD OF DETECTING OVERLAY ALIGNMENT ERROR USING THE MARK - A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values. | 02-07-2013 |