Patent application number | Description | Published |
20130201462 | METHOD OF DETERMINING OVERLAY ERROR AND CONTROL SYSTEM FOR DYNAMIC CONTROL OF RETICLE POSITION - A method of determining overlay error. The method includes transferring a pattern from a reticle to a wafer and selecting a first set of data points to measure the positional difference between features on the reticle and features on the wafer. The method also includes determining a second set of data points characteristic of the first set of data points but containing fewer data points. A control system for using the second set of data points to dynamically adjust the position of the reticle. | 08-08-2013 |
20130252175 | Litho Cluster and Modulization to Enhance Productivity - The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process. | 09-26-2013 |
20130258339 | WAFER ALIGNMENT MARK SCHEME - A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to a backside of the wafer. The light detection device is configured to detect reflected light intensity from the backside of the wafer to find a position of at least one wafer alignment mark formed on the back side of the wafer. | 10-03-2013 |
20130285264 | WAFER ASSEMBLY WITH CARRIER WAFER - A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark. | 10-31-2013 |
20130286395 | Tool Induced Shift Reduction Determination for Overlay Metrology - One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements. | 10-31-2013 |
20130293857 | LITHOGRAPHY APPARATUS HAVING DUAL RETICLE EDGE MASKING ASSEMBLIES AND METHOD OF USE - A lithography apparatus includes at least two reticle edge masking assemblies (REMAs). The lithography apparatus further includes a light source configured to emit a light beam having a wavelength and a beam separating element configured to divide the light beam into more than one collimated light beam. Each REMA is positioned to receive one of the more than one collimating light beams and each REMA comprises a movable slit for passing the one collimated light beam therethrough. The lithography apparatus further includes at least one mask having a pattern, where the at least one mask is configured to receive light from at least one of the REMA and a projection lens configured to receive light from the at least one mask. A method of using a lithography apparatus is also discussed. | 11-07-2013 |
20130309612 | ENHANCED SCANNER THROUGHPUT SYSTEM AND METHOD - A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned. | 11-21-2013 |
20140017604 | LITHOGRAPHY PROCESS - A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer. | 01-16-2014 |
20140240706 | OVERLAY SAMPLING METHODOLOGY - A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies. | 08-28-2014 |
20140328534 | DETECTION OF DEFECTS ON WAFER DURING SEMICONDUCTOR FABRICATION - Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to generate a projection. In some embodiments, the non-correctable error image map is transformed via a feature extraction transform such as a Hough transform or a Radon transform. In some embodiments, the projection is compared to a set of rules to identify a signature in the non-correctable error image map indicative of a defect. | 11-06-2014 |
20140362359 | FLEXIBLE WAFER LEVELING DESIGN FOR VARIOUS ORIENTATION OF LINE/TRENCH - The present disclosure relates to a photolithography system having an ambulatory projection and/or detection gratings that provide for high quality height measurements without the use of an air gauge. In some embodiments, the photolithography system has a level sensor having a projection source that generates a measurement beam that is provided to a semiconductor substrate via a projection grating. A detector is positioned to receive a measurement beam reflected from the semiconductor substrate via a detection grating. An ambulatory element selectively varies an orientation of the projection grating and/or the detection grating to improve the measurement of the level sensor. By selectively varying an orientation of the projection and/or detection gratings, erroneous measurements of the level sensor can be eliminated. | 12-11-2014 |
20150015870 | Overlay Abnormality Gating by Z Data - The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process. | 01-15-2015 |
20150076371 | LITHO CLUSTER AND MODULIZATION TO ENHANCE PRODUCTIVITY - The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process. | 03-19-2015 |