| Patent application number | Description | Published |
|---|
| 20080290406 | METHOD FOR PRODUCING A VERTICAL FIELD EFFECT TRANSISTOR - A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility. | 11-27-2008 |
| 20080296703 | Method for Producing a Field-Effect Transistor, Field-Effect Transistor and Integrated Circuit Arrangement - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 12-04-2008 |
| 20090072388 | SEMICONDUCTOR DEVICE WITH INDUCTOR - One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip. | 03-19-2009 |
| 20090073633 | SEMICONDUCTOR DEVICE WITH CAPACITOR - One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer. | 03-19-2009 |
| 20090236647 | SEMICONDUCTOR DEVICE WITH CAPACITOR - An embodiment of the invention is a semiconductor structure, comprising: a semiconductor chip at least partially embedded within a support; and a capacitor disposed outside the lateral boundary of the chip, the capacitor electrically coupled to the chip. | 09-24-2009 |
| 20100001373 | CORRESPONDING CAPACITOR ARRANGEMENT AND METHOD FOR MAKING THE SAME - The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability. | 01-07-2010 |
| 20100264472 | PATTERNING METHOD, AND FIELD EFFECT TRANSISTORS - A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor. | 10-21-2010 |
| 20110012208 | FIELD-EFFECT TRANSISTOR WITH LOCAL SOURCE/DRAIN INSULATION AND ASSOCIATED METHOD OF PRODUCTION - A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. | 01-20-2011 |
