| Patent application number | Description | Published |
|---|
| 20080239788 | INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD - An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage. | 10-02-2008 |
| 20080259676 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product - According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell. | 10-23-2008 |
| 20080263415 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System - According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells. | 10-23-2008 |
| 20090122586 | METHOD AND APPARATUS FOR AN INTEGRATED CIRCUIT WITH PROGRAMMABLE MEMORY CELLS, DATA SYSTEM - A method and apparatus for an integrated circuit with programmable memory cells which are arranged between a first and a second conductor for supplying first and second voltage is provided. A control circuit is arranged between the memory cells and the second conductor. The control circuit controls a change time during which at least one of the memory cells is supplied with a changing current from the second supply changing a state of the memory cell. The control circuit senses the state of the memory cell and stops the erasing current when the memory cell is in a changed state. Furthermore an embodiment refers to a data system with a programmable memory and a method of operating an integrated circuit. Another embodiment refers to a method of operating an integrated circuit. | 05-14-2009 |
| 20090201714 | RESISTIVE MEMORY CELL AND METHOD FOR OPERATING SAME - An integrated circuit comprising at least one resistive memory cell, comprising a resistive memory element and a selection device, said resistive memory element having at least two resistive OFF-states, each OFF-state defining a predefined resistance value is described. Moreover, a memory, a computing system and method of operating a memory are described. | 08-13-2009 |
| 20090207646 | INTEGRATED CIRCUIT WITH RESISTIVE MEMORY CELLS AND METHOD FOR MANUFACTURING SAME - An integrated circuit including a resistive memory cell and a method of manufacturing the integrated circuit are described. The integrated circuit comprises a plurality of resistive memory cells and a plurality of voltage supply contacts, wherein at least four resistive memory cells are in signal connection with one voltage supply contact. | 08-20-2009 |
| 20090213643 | Integrated Circuit and Method of Improved Determining a Memory State of a Memory Cell - According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the first potential, thereby generating a memory state sensing current flowing through the resistivity changing memory cell; controlling the strength of the second potential in dependence on the strength of the memory state sensing current such that the strength of the memory state sensing current is kept constant. | 08-27-2009 |
| 20090257264 | MEMORY AND METHOD OF EVALUATING A MEMORY STATE OF A RESISTIVE MEMORY CELL - An integrated circuit comprises a first signal line, a second signal line and a resistive memory cell. The resistive memory cell is actively connectable to the first signal line. The integrated circuit further comprises a coupling device configured to generate a difference of potential between the first and second signal line when the resistive memory cell is actively connected to the first signal line. | 10-15-2009 |
| 20100058018 | Memory Scheduler for Managing Internal Memory Operations - An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller. | 03-04-2010 |
