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Heineck
Lars Heineck, Radebeul DE
| Patent application number | Description | Published |
|---|---|---|
| 20090302380 | Word Line to Bit Line Spacing Method and Apparatus - In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line. | 12-10-2009 |
| 20100090264 | INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES - One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed. | 04-15-2010 |
Lars Heineck, Radebehl DE
| Patent application number | Description | Published |
|---|---|---|
| 20100090348 | Single-Sided Trench Contact Window - An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls. | 04-15-2010 |
Lars Heineck, Dresden DE
| Patent application number | Description | Published |
|---|---|---|
| 20080299722 | Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure - The present invention provides a method for forming a recessed channel transistor comprising the steps of: | 12-04-2008 |
| 20080315326 | Method for forming an integrated circuit having an active semiconductor device and integrated circuit - An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed. | 12-25-2008 |
Lars Heineck, Garden City, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20120104491 | Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed. | 05-03-2012 |
Matthew P. Heineck, Corvallis, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20110080454 | Firing Cell - A system is provided that includes first means for pre-charging a node to a first potential where the node coupled to a switch configured to control current through a firing resistor and second means for selectively discharging the node to a second potential across a path that has only one transistor between the node and the second potential. | 04-07-2011 |
Tobias Heineck, Durham, NC US
| Patent application number | Description | Published |
|---|---|---|
| 20090178370 | Devices and Methods for Verifying Capping of Vials in System for Dispensing Prescriptions - A method of verifying the seating and securing of a closure on a container includes the steps of: (a) positioning a container on a stage of an automated capping station; (b) bringing a closure into contact with the container; (c) detecting the nature of a physical relationship between the container and the closure; (d) responsive to step(c), relatively moving the closure and the container if step (c) indicates seating of the closure on the container is proper; and (e) detecting the nature of a physical relationship between the closure and the container to determine whether the closure is properly secured. | 07-16-2009 |
| 20110305545 | System and Method for High-Volume Filling of Pharmaceutical Prescriptions - A method of retrieving a vial from a carrier includes the steps of: contacting a vial contained within a carrier with a gripper assembly to shift the position of the container to one end of the carrier and to adjust the position of the carrier on a platform from a diverted position to a retrieval position; lifting the vial from the carrier with the gripper assembly; and returning the vial to the carrier with the gripper assembly. Such a method can improve the accuracy and precision of moving the vial to and from the carrier for dispensing. | 12-15-2011 |