Patent application number | Description | Published |
20080315406 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE - An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction integrated circuit package in the base substrate cavity, and attaching a base integrated circuit over the junction integrated circuit package and the base substrate. | 12-25-2008 |
20100224975 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL BOARD-ON-CHIP STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation. | 09-09-2010 |
20100237481 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: attaching an integrated circuit having a through via over a substrate with the through via coupled to the substrate; attaching a conductive support over the substrate and adjacent to the integrated circuit; forming an encapsulation over the substrate with the conductive support exposed from the encapsulation; and attaching an external interconnect under the substrate. | 09-23-2010 |
20100237483 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit. | 09-23-2010 |
20100237500 | Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site - A semiconductor substrate includes a first conductive layer formed over the semiconductor substrate. The first conductive layer has first and second portions which are electrically isolated during formation of the first conductive layer. A solder resist layer is formed over the first conductive layer and semiconductor substrate. An opening is formed in the solder resist layer to expose the first conductive layer. A seed layer is formed over the semiconductor substrate and first conductive layer within the opening. A second conductive layer is formed over the seed layer within the opening. The opening may expose the second portion of the first conductive layer due to solder resist registration shifting causing a defect condition. The second conductive layer electrically contacts the first and second portions of the first conductive layer. By testing the first and second portions of the first conductive layer, the defect condition can be identified. | 09-23-2010 |
20100244222 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an internal-interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate with the integral-interposer-structure connected to the internal-interconnect; mounting an integrated circuit to the substrate and under the integral-interposer-structure; and encapsulating the internal-interconnect and the integrated circuit with an encapsulation. | 09-30-2010 |
20100258928 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a first integrated circuit to the substrate by interconnects only along opposite sides of the first integrated circuit; and attaching a heat spreader to the substrate, the heat spreader extending over the first integrated circuit and between the opposite sides of the first integrated circuit. | 10-14-2010 |
20100276792 | Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure - A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer. | 11-04-2010 |
20110298105 | Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure - A method of manufacturing a semiconductor device includes providing a substrate having a conductive bump formed over the substrate and a semiconductor die with an active surface oriented to the substrate. An encapsulant is deposited over the semiconductor die and the conductive bump, and the encapsulant is planarized to expose a back surface of the semiconductor die opposite the active surface while leaving the encapsulant covering the conductive bump. A channel is formed into the encapsulant to expose the conductive bump. The channel extends vertically from a surface of the encapsulant down through the encapsulant and into a portion of the conductive bump. The channel extends through the encapsulant horizontally along a length of the semiconductor die. A shielding layer is formed over the encapsulant and the back surface of the semiconductor die. The shielding layer includes a docking pin extending into the channel and into the portion of the conductive bump to electrically connect to the conductive bump and provide isolation from inter-device interference. | 12-08-2011 |
20120038034 | Semiconductor Device and Method of Forming Vertical Interconnect in FO-WLCSP Using Leadframe Disposed Between Semiconductor Die - A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe. | 02-16-2012 |
20130026654 | Semiconductor Device and Method of Forming Vertical Interconnect in FO-WLCSP Using Leadframe Disposed Between Semiconductor Die - A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe. | 01-31-2013 |